Dual gate multi-bit semiconductor memory array

Details Dual gate multi-bit semiconductor memory array Dual gate multi-bit semiconductor memory array

2011-03-08

2011-03-08

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29309

Reexamination Certificate

active

07902589

ABSTRACT:
An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns of the memory cells, where each control line connects to the first gate of the memory cell in the corresponding column in each of the rows; and one or more word lines, each of which corresponds to one of the rows of the memory cells, where each word line connects to the second gate of each of the cells in the corresponding row.

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