Dual gate LDMOSFET device for reducing on state resistance

Details Dual gate LDMOSFET device for reducing on state resistance Dual gate LDMOSFET device for reducing on state resistance

1991-03-20

1993-09-07

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

257328, 257339, 257342, 307571, 307573, 307585, H03K 1708, H03K 1714, H03K 17687, H01L 29784

Patent

active

052432343

ABSTRACT:
A double polysilicon dual gate LDMOSFET structure combined with a detecting circuit can be used to reduce the ON state resistance and without degradation of the breakdown voltage of the LDMOSFET. In the ON state, a drift region is driven into accumulation. In the OFF state, a gate is made to float and thereby avoid degradation of the breakdown voltage. A switch or transistor is modulated to either allow applied voltage to bias the gate for enabling the drift region to be driven into accumulation or to cause the gate to float to prevent the driving of the drift region by the voltage.

REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4366495 (1982-12-01), Goodman et al.
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4942440 (1990-07-01), Baliga et al.
patent: 4952991 (1990-08-01), Kayama

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