Dual-gate integrated circuit semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21625, C257SE21639

Reexamination Certificate

active

11343680

ABSTRACT:
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

REFERENCES:
patent: 5254489 (1993-10-01), Nakata
patent: 5960289 (1999-09-01), Tsui et al.
patent: 6479400 (2002-11-01), Suzuki
patent: 6653192 (2003-11-01), Ryoo
patent: 2004/0067619 (2004-04-01), Niimi

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