Dual-gate dynamic logic circuit with pre-charge keeper

Details Dual-gate dynamic logic circuit with pre-charge keeper Dual-gate dynamic logic circuit with pre-charge keeper

2007-11-20

2007-11-20

Le, Don (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S027000

Reexamination Certificate

active

11204401

ABSTRACT:
A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

REFERENCES:
patent: 6204696 (2001-03-01), Krishnamurthy et al.
patent: 6429684 (2002-08-01), Houston
patent: 6600340 (2003-07-01), Krishnamurthy et al.
Keunwoo, et. al., “Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices,”IEEE Transaction on Electron Devices, vol. 48, No. 2, Feb. 2001, pp. 294-299.
Chiang, et. al., “Novel High-Density Low-Power High-Performance Double-Gate Logic Techniques,”2004 IEE International SOI Conference, Charleston, SC, Oct. 4-7, 2004, pp. 122, 123.
“Taurus-MEDICI, Industry-Standard Device Simulation Tool,” Mountain View, CA,Synopsis, Inc., 2003, pp. 1-7, no month.

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