Dual gate dielectric construction

Details Dual gate dielectric construction Dual gate dielectric construction

2001-06-12

2003-11-25

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S411000

Reexamination Certificate

active

06653675

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to gate dielectrics for integrated circuit transistors. More particularly, the invention relates to processes and structures for optimizing the thickness of gate dielectrics.
2. Description of the Related Technology
In the field of integrated circuit fabrication, current leakage through thin dielectric layers presents a continuing challenge to device integration. Leakage through gate dielectrics of field effect transistors (FETs) is known as Fowler-Nordheim currents, while gate induced diode leakage (GIDL) occurs at the edge of the gate electrode. As the gate dielectrics, which are typically formed of silicon oxide, become increasingly thinner due to continued scaling of integrated circuits in pursuit of faster and more efficient circuit operation, GIDL occurs even during transistor off states.
Certain integrated devices, such as transistors within memory arrays of a dynamic random access memory (DRAM), are particularly sensitive to GIDL. Moreover, significant transistor GIDL can induce leakage at storage nodes of a memory array. Accordingly, gate oxides in memory arrays must be effective at resisting GIDL for proper operation.
Transistors leakage tends to occur at gate edges, where electric fields are concentrated. Accordingly, one partial solution to the problem of GIDL, where conventional oxides are used for the gate dielectric, is to perform a re-oxidation process. The re-oxidation is performed after forming gate electrodes, such that the gate oxide edges under the gate electrode corners are thickened relative to the remainder of the gate oxide dielectric. However, metals used in word lines (part of which form the gate electrodes) are susceptible to degradation during the re-oxidation process. Recently popular word line materials, such as tungsten, are particularly susceptible to oxidation.
Peripheral circuits of a DRAM chip generally include logic circuits, such as address decoders and read/write control circuits. These logic circuits in the periphery of the memory chip, in contrast to memory array transistor, require faster transistor switching times. Such aggressive operation is facilitated by thinner gate oxides in these peripheral circuits. Logic circuits also tolerate a higher GIDL current, as compared to memory arrays, such that thinning gate oxides within the peripheral areas may be feasible from a GIDL standpoint.
In order to accommodate the differing needs of the memory array and peripheral circuits, the circuit design can include two or more different thicknesses of gate oxide on the same silicon substrate. According to the prior art, different thicknesses of gate oxide have been formed by selective oxidation through an existing thin oxide layer (in areas which require thick oxides), or by selective etching of an existing oxide layer (in areas which require thinner oxides). Either selective oxidation or etching, require at least one additional mask, which increases the cost of fabrication.
Moreover, thin gate oxides in field effect transistors are more easily worn out due to the injection of hot electrical carriers through the channel which is formed below the thin oxide. Such oxide wear out may reduce reliability, yield and/or life span of the device.
Therefore, a need exists for processes and structures which address the various needs of memory arrays and logic circuits.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an integrated circuit is provided. The circuit includes a semiconductor substrate with adjacent first and second areas, and first and second transistors gate electrodes are formed over the first and second areas, respectively. A first gate dielectric, including a non-oxide material, is positioned between the first transistor gate electrode and the substrate in the first area. A second gate dielectric is positioned between the second transistor gate electrode and the substrate in the second area. Where x represents the equivalent oxide thickness of the first gate dielectric, the second gate dielectric has an equivalent oxide thickness of at least about 1.1x.
In accordance with another aspect of the invention, a system is pro vided with a semiconductor substrate, including first and second transistors. Each of the first transistors has a first gate insulator, including silicon nitride, and each of the second transistors has a second gate insulator formed of silicon oxide.
In accordance with another aspect of the invention, an integrated memory chip is provided. The chip includes logic circuits and memory array circuits on a semiconductor substrate. Transistor gate dielectrics in the logic circuits include a layer of a first material, while transistor gate dielectrics in the memory array circuits are formed of a second material. The dielectric constant of the first material is different from the dielectric constant of the first material.
In accordance with still another aspect of the invention, a memory chip is provided with at least one memory array and a logic circuit. The memory array has array gate electrodes separated from a semiconductor substrate by a gate oxide. The logic circuit has logic gate electrodes separated from the substrate by an gate dielectric, which includes silicon nitride and silicon oxide. The equivalent oxide thickness of the gate oxide is greater than the equivalent oxide thickness of the gate dielectric.
In accordance with another aspect of the invention, a process is disclosed for optimizing gate insulator characteristics in different regions of an integrated circuit formed in a semiconductor substrate. The process includes forming a non-oxide dielectric layer over a first region of the substrate. An oxide layer is grown through the non-oxide dielectric layer in the first region of the substrate. Simultaneously, an oxide layer is grown in an exposed second region of the substrate, which is situated adjacent the first region.
In accordance with yet another aspect of the invention, a method is disclosed for fabricating a memory chip. Logic circuit and memory array regions are defined in a substrate. A silicon nitride layer is deposited over the substrate in both regions. A mask is formed over the silicon nitride layer in the logic circuit region, and a portion of the silicon nitride layer removed from the substrate in the memory array region. Then the mask is removed, followed by an oxidation.


REFERENCES:
patent: 4627153 (1986-12-01), Masuoka
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4675982 (1987-06-01), Noble, Jr. et al.
patent: 4957878 (1990-09-01), Lowrey et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5101251 (1992-03-01), Wakamiya et al.
patent: 5264724 (1993-11-01), Brown et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5360769 (1994-11-01), Thakur et al.
patent: 5376593 (1994-12-01), Sandhu et al.
patent: 5393683 (1995-02-01), Mathews et al.
patent: 5395786 (1995-03-01), Hsu et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5407870 (1995-04-01), Okada et al.
patent: 5463234 (1995-10-01), Toriumi et al.
patent: 5502009 (1996-03-01), Lin
patent: 5658811 (1997-08-01), Kimura et al.
patent: 5668035 (1997-09-01), Fang et al.
patent: 5731238 (1998-03-01), Cavins et al.
patent: 5843817 (1998-12-01), Lee et al.
patent: 5863819 (1999-01-01), Gonzalez
patent: 5960289 (1999-09-01), Tsui et al.
patent: 5966618 (1999-10-01), Sun et al.
patent: 6033998 (2000-03-01), Aronowitz et al.
patent: 6037224 (2000-03-01), Buller et al.
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6136728 (2000-10-01), Wang
patent: 08031958 (1996-02-01), None
Sekine et al., “Self-aligned tungsten strapped source/drain and gate technology realizing the lowest sheet resistance for sub-quarter micron CMOS,” International Electron Devices Meeting, Dec. 1994, IEEE, p. 493-496.*
S. Shimizu, et al., “Impact of Surface Proximity Gettering and Nitrided Oxide Side-Wall Spacer by Nitrogen Implantation on Sub-Quarter Micron CMOS LDD FETs,” IEDM 1995, pp. 859-862.

Affiliated with

Also associated with

Rating

Dual gate dielectric construction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual gate dielectric construction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual gate dielectric construction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3130451