Dual gate CMOS fabrication

Details Dual gate CMOS fabrication Dual gate CMOS fabrication

2005-08-01

2010-02-09

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S573000, C438S588000, C438S660000, C257SE21156

Reexamination Certificate

active

07659154

ABSTRACT:
The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

REFERENCES:
patent: 6255204 (2001-07-01), Tobin et al.
patent: 6518154 (2003-02-01), Buynoski et al.
patent: 7316950 (2008-01-01), Park et al.
patent: 7528024 (2009-05-01), Colombo et al.
patent: 2004/0245578 (2004-12-01), Park et al.
patent: 2005/0258468 (2005-11-01), Colombo et al.
patent: 2006/0128125 (2006-06-01), Mangelinck et al.
patent: WO 2004095572 (2004-11-01), None

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