Dual functioning symbol error correction code

Details Dual functioning symbol error correction code Dual functioning symbol error correction code

1999-10-13

2003-03-25

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S781000

Reexamination Certificate

active

06539513

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to error correcting codes, and, more particularly to a single error correcting code that incorporates two codes into one.
BACKGROUND OF THE INVENTION
Error correcting codes (ECC) have been routinely used for fault tolerance in computer memory subsystems. The most commonly used codes are the single error correcting (SEC)-double error detecting (DED) codes capable of correcting all single errors and detecting all double errors in a code word. These SEC-DED codes are most effective in protecting memory data when the memory array chips are configured in one-bit-per-chip with respect to the ECC words. When memory chips are configured in b-bits-per-chip, a failing chip may generate from 0 to b bits of a data block, depending on the failure modes of the chip and the stored data. A b-bit error pattern generated from a chip failure is called a “symbol error.” An SEC-DED code is not capable of correcting or detecting symbol ECC, error correcting codes designed for detecting and correcting symbol errors, would be more effective in providing fault tolerance for b-bits-per-chip memory applications.
As the trend of chip manufacturing is toward a larger chip capacity, more and more memory subsystems will be configured in b-bits-per-chip. The most appropriate symbol ECC to use on the memory are the single symbol error correcting (SSC) and double symbol error detecting (DSD) codes that correct all single symbol errors and detect all double symbol errors in a code word. A memory designed with an SSC-DSD code can continue to function when a memory chip fails, regardless of its failure mode. When there are two failing chips that line up in the same ECC word sometime later, the SSC-DSD code would provide the necessary error detection and protect the data integrity for the memory.
For a memory array configured in b-bit-per-chip, the ability for an ECC to correct multi-bit errors (symbol errors) generated from single chip failures is important in the ECC design. For memory reliability and for data integrity, the class of SSC-DSD codes should be used, where a symbol error is a b-bit error pattern that can be generated from a chip failure in an b-bit-per-chip memory configuration.
Normally, two separate ECCs have to be used for two different memory configurations. For example, a (
144
,
132
) SSC-DSD code for a two-bit-per-chip memory and a (
148
,
132
) SSC-DSD code for a four-bit-per-chip memory.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for constructing a single ECC that incorporates two codes into one is presented. This single ECC design can be applied to a memory configured in 2-bit-per-chip or 4-bit-per-chip. A mode bit M is used to indicate one of the two memory configurations. When M is 0, the ECC functions as a (
144
,
132
) SSC-DSD code with 132 data bits and 12 check bits. When M is 1 the ECC functions as a (
148
,
132
) SSC-DSD code with 132 data bits and 16 check bits. The allocated 132 data bits may consist of 128 data bits that are actually stored in the memory and 4 other bits that are not required to be stored in the memory, e.g., parities of memory address bits. For an application where the actual number of data bits is less than the allocated 132 bits, the unused data bits can be ignored or set to zero in the ECC implementation.


REFERENCES:
patent: 5745507 (1998-04-01), Chen
patent: 5757823 (1998-05-01), Chen et al.
patent: 6009548 (1999-12-01), Chen et al.
Symbol Error Correcting Codes for Memory Application, C. L. Chen, Proceedings of the Twenty-Sixth International Symposium on Fault-Tolerant Computing, Jun. 25-27, 1996, pp. 201-207.
A System Solution to Reducing Frequency of Memory Repairs, C. L. Chen and M. Y. Hsiao, Proceedings Pacific Rim International Symposium on Fault-Tolerant Systems, Dec. 15-16, 1997, pp. 53-58.

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