Computer graphics processing and selective visual display system – Computer graphics display memory system – Cache
Reexamination Certificate
1999-07-30
2002-08-13
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Cache
C345S614000
Reexamination Certificate
active
06433788
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to video graphics processing and more particularly to a dual cache pixel processing circuit and method therefore.
BACKGROUND OF THE INVENTION
Computer displays and other high resolution display devices such as high definition television (HDTVs), projectors, printers, plotters, and the like, present an image to the viewer as an array of individual picture elements, or pixels. The individual pixels are each given a specific color that corresponds to the color of the image at the location at the particular pixel. The pixels are closely spaced, and the viewer's visual system performs a filtering of the individual pixel colors to form a composite image. If the partitioning of the image into the individual pixel elements is performed properly and the pixels are close enough together, the viewer perceives the displayed array of pixels as a virtually continuous image.
Images are drawn to the display through the use of graphics primitives, which are often triangle primitives. These primitives are processed by the graphics processing system to produce individual pixel fragments. A pixel fragment is a fragment of the video graphics primitive. Each fragment determines a particular color and Z value corresponding to the primitive as applied to a particular pixel location on the display. Pixel fragments are typically processed by a render backend block. The render backend block determines the pixel to which the fragment corresponds and fetches current pixel information for that pixel location from a frame buffer that stores the pixel data for each pixel in the frame. The render backend block then performs blending operations that combine the received fragments with the currently stored information for the corresponding pixel locations in the frame buffer and write the new pixel information resulting from the blending operations back to the frame buffer.
Multiple graphics primitives may be processed in quick succession where each of the multiple graphics primitives produces fragments that correspond to the same pixel location. As such, rather than forcing the render backend block to handle multiple fragments corresponding to the same pixel location, a cache structure can be used to buffer the received fragments prior to providing them to the render backend block. Including a cache structure in the data path for the pixel fragments enables multiple fragments that apply to the same pixel location to be combined prior to presentation to the render backend block. Offloading some of the blending operations from the render backend block can improve overall system performance.
When performing drawing operations, the render backend block typically relies on certain state parameters. Examples include alpha blending and a parameter that orients fragments spatially with respect to the Z access. When a state change occurs in the system such that some of the state parameters are altered, the cache can cause problems in the flow of received fragments. The pixel fragments stored in the cache prior to the state change are fragments that should be blended by the render backend block using the old state parameters, whereas fragments subsequently received rely on the new state parameters. As such, the entire cache must be flushed and the fragments provided to the render backend block with the old state parameters before additional fragments can be received. Halting the incoming stream of fragments can adversely affect the video graphics processing operations, and defeats some of the improved performance obtained by including a cache in the fragment data path.
Therefore, a need exists for a method and apparatus that allows for caching of pixel fragments while ensuring that state changes do not adversely affect video graphics processing performance.
REFERENCES:
patent: 5909225 (1999-06-01), Schinnerer et al.
patent: 5990904 (1999-11-01), Griffin
patent: 6115049 (2000-09-01), Winner et al.
patent: 6204856 (2001-03-01), Wood et al.
ATI International SRL
Chauhan Ulka J.
Vedder Price Kaufman & Kammholz
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