Dual-edge fifo interface

Details Dual-edge fifo interface Dual-edge fifo interface

2000-05-12

2004-11-02

Jean, Frantz B. (Department: 2151)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S055000, C710S057000, C710S052000, C710S309000, C710S310000, C711S131000, C711S149000

Reexamination Certificate

active

06813674

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains generally to the field of computer system power management, and more particularly to a distributed power management system and method wherein power management functions are delegated to individual modular subsystems or functional components within the overall computer system.
BACKGROUND OF THE INVENTION
Power management has been, and continues to be, a major concern in the development and implementation of battery powered or battery operated microprocessor based systems, such as laptop computers, notebook computers, palmtop computers, personal data assistants (PDAs), hand-held communication devices, wireless telephones, and any other devices incorporating microprocessors in a battery-powered unit, including units that are occasionally battery powered, but that also operate from a power line (AC) source. The need for power management is particularly acute for battery-operated single-chip microcomputer systems, where the desirability or requirement for overall reduction in physical size (and/or weight) also imposes severe limits on the size and capacity of the battery system, and yet where extending unit operating time without sacrificing performance is a competing requirement. Conventional methods for power managing these types of systems have typically been based on a centralized power management unit architecture.
For example, in an exemplary conventional centralized power management unit
20
, such as that illustrated in
FIG. 1
, an activity monitor
21
, monitors accesses to specific system resources, such as access to serial ports
31
, parallel ports
32
, a display subsystem controller
33
, memory controller
34
, keyboard controller
35
, and like resources. Such activity monitor
21
may be implemented in hardware or software, and in either case may be configured (such as by hard wiring, firmware, or software) to accommodate specification of a particular system resource address range or ranges to be monitored. The centralized power management unit (PMU) passively watches activity on the bus concerning other system resource units. The occurrence of one or more pre-identified addresses or address ranges on address bus
26
is recognized by the activity monitor, which in turn operates to trigger a particular predetermined action, such as to alter the operating state or mode of one or more system devices to affect a change in the power consumption state of the system.
In one conventional power management system, five operating states are provided: ON, DOZE, SLEEP, SUSPEND, and OFF. These names are not uniformly standardized, but each of the DOZE, SLEEP, and SUSPEND modes represents intermediate power consumption states between fully ON and fully OFF. By way of example, under one set of rules, in the ON state, the bus clock may operate at full speed, the LCD display system may be ON, memory may be ON, and the system as a whole may be ON. In the DOZE state, the bus clock may be slowed or stopped, the LCD is ON, memory is ON, and the system is ON. The SLEEP state provides a bus clock which is either slow or stopped, as compared to the full speed bus clock, the liquid crystal display is OFF, memory remains ON, and the system as a whole remains ON and responsive. In the SUSPEND state, the bus clock is typically stopped, the liquid crystal display is OFF, memory is ON, but the system as a whole is OFF. Maintaining memory in the ON state is important for rapid resumption of processing, such as when a keyboard key is struck by a user to reinitiate input processing on the computer system. Finally, in the OFF state, the bus clock is stopped and the subsystem power supply to the LCD, memory, and system are OFF.
Other conventional centralized power management systems may implement more or fewer states or power consumption modes, and such systems may control power delivery to devices and/or modify clock frequency.
Activity masks
22
may also be provided, and, when present, permit control of which of the monitored system resources will generate an activity indicator when accessed. Such activity indicators are used to control transitions of the computer from one state to another, such as, for example, in the context of the exemplary system described above, a transition from SLEEP state to the DOZE state, or the ON state, in response to a user of the computer making a keyboard key entry. When activity masks are implemented, those resources which are to be monitored for activity are unmasked, and those resources which may be ignored and are not monitored are masked. Some implementations provide a unique activity mask for each power management state.
Activity timers
23
may also be provided. The activity timers are typically initialized by software to specify the amount of “idle” time which may be allowed to elapse before moving to the next (typically lower) power consumption state. The value of the idle time may typically vary for each power state or state transition, but tends to be defined as the following order of magnitude timings: a power state transition from ON to DOZE is implemented with a first idle time of between about 1 millisecond (1×10
−3
seconds) and some small number of seconds, for example, from about 1 to about 30 seconds. The transition from a DOZE state to a SLEEP state is typically implemented with a second idle time of seconds to one or a few minutes. And, the power state transition from SLEEP to SUSPEND state is typically implemented with a third idle time of a few minutes to several minutes. U.S. Pat. No. 5,396,635 herein incorporated by reference, includes a description of one particular power management system which has an activity monitor, and uses activity masks and activity timers.
Note that for a microprocessor operating at 200 MHZ, each clock cycle represents 5.0 nanoseconds (5×10
−9
sec), and for a system bus operating at a 100 MHZ clock, each clock cycle represents 10 nanoseconds. Furthermore, it is noted that external memory access typically requires 40-60 nanoseconds, while internal memory may operate at the microprocessor clock rate. It is therefore easily appreciated that even the shortest conventional idle period of, for example 1 millisecond, is long compared to a system bus cycle (10 nanoseconds) by a factor of 10
5
.
In conventional computer power management systems, one activity timer, or timer value, is normally allocated per power management state. When unmasked activity is detected, the activity timer is reloaded or reset with the “time out” timing value programmed by software. Then, when the activity timer for a particular power management state expires, either an interrupt is generated to allow software to control the transition to the next power management state, or the transition occurs automatically by hardware control.
Transition from a lower power consumption state to higher power consumption state may occur relatively more quickly. For example, the operating state may transition directly from the SUSPEND state upon detection of a single keyboard key entry to the ON state, or such change may require a plurality of events for such transition to occur.
With further reference to
FIG. 1
, the power state block
24
controls the system power management state and interfaces to the clock control logic
25
. Clock control logic block
25
receives a clock input signal (clock_in) at a first clock frequency (f
1
) and controls the state of the output bus clock. Clock control
25
may pass the clock_in signal through, may slow the clock to a lower frequency (f
2
), or may stop the bus clock for the entire system during certain low power consumption power management states. State transitions can be initiated by software, or can occur automatically in hardware when an activity timer expires.
Centralized power management architecture, such as that exemplified by the system in
FIG. 1
, has the disadvantage that, when the system is operating in a reduced power consumption state, an access to any unmasked system resource typically causes an exit (state transition) from that re

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