Dual-edge extended data out memory

Details Dual-edge extended data out memory Dual-edge extended data out memory

1997-06-19

1999-09-07

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711 5, 711167, 36523003, 365193, G06F 1200

Patent

active

059502231

ABSTRACT:
A memory is modified so that read and write data are transferred on both rising and falling edges of a timing signal, thereby essentially doubling the data transfer rate from memory. In one embodiment, a dual-edge extended data out (DE.sup.2 DO) memory includes modified and improved circuits and operating methods, as compared to a standard extended data out (EDO) memory, so that read and write data are transferred on both rising and falling edges of a timing signal. In a described embodiment, DE.sup.2 DO dynamic RAM (DRAM) reads and writes data on the rising and falling edges of a column address strobe (CAS) timing signal. By transferring data on both the rising and falling edges of the timing signal, the data transfer rate to and from the memory is effectively doubled.

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patent: 5341488 (1994-08-01), Kobayashi
patent: 5479635 (1995-12-01), Kametani
patent: 5729709 (1998-03-01), Harness
"64Mb DDR SDRAM"; Samsung Semiconductor Inc, North America; http://www.usa.samsungsemi.com
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Prince, Betty. "High Performance Memories New Architecture DRAMs and SRAMs-evolution and function"; John Wiley & Sons; Dec. 1996; pp. 205-209.
"Draft Standard for A High-Speed Memory Interface (SyncLink)"; IEEE Standards Department; Dec. 1996.

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