Dual edge command in DRAM

Details Dual edge command in DRAM Dual edge command in DRAM

2007-11-20

2007-11-20

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000, C711S220000

Reexamination Certificate

active

10767555

ABSTRACT:
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

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