Dual edge clock address mark detector

Details Dual edge clock address mark detector Dual edge clock address mark detector

1985-05-23

1986-11-25

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

328120, 360 51, H04K 102

Patent

active

046253211

ABSTRACT:
A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.

REFERENCES:
patent: 3382492 (1968-05-01), Santana
patent: 4053944 (1977-10-01), Dixon
patent: 4072990 (1978-02-01), Case et al.

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