Dual edge adjusting digital phase-locked loop having one-half re

Details Dual edge adjusting digital phase-locked loop having one-half re Dual edge adjusting digital phase-locked loop having one-half re

1995-05-16

1996-08-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 34, 331 1A, H03D 324

Patent

active

055464343

ABSTRACT:
A digital phase-locked loop having a jitter limited to one-half of a period of the reference clock comprises a generator circuit and a control circuit. The input clock is defined by a plurality of rising edges and falling edges. The generator circuit receives a reference clock and generates the output clock. The phase of the output clock is one of a plurality of selectable phases such that the difference in phases between the output clock and the input clock is limited to one-half of a period of the reference clock once the DPLL locks to the input clock. The control circuit receives the input clock, the reference clock, and the output clock and provides a selection input to the generator circuit to make the phase of the output clock selectable upon each rising edge and upon each falling edge of the input clock.

REFERENCES:
patent: 4617679 (1983-09-01), Brooks
patent: 5036297 (1991-07-01), Nakamura
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5218314 (1992-05-01), Efendovich et al.
patent: 5355092 (1994-10-01), Kosaka et al.
patent: 5428648 (1995-06-01), Fukuda

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