Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2011-07-12
2011-07-12
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000
Reexamination Certificate
active
07979746
ABSTRACT:
Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.
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Cornelius Brian
Fletcher Mitch
Ross James Alexander
Scheid David
Honeywell International , Inc.
Ingrassia Fisher & Lorenz P.C.
Le Dieu-Minh
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