Dual-die integrated circuit package

Details Dual-die integrated circuit package Dual-die integrated circuit package

2002-03-06

2004-01-13

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S690000, C257S669000, C257S784000, C257S723000, C257S674000, C257S782000, C257S787000

Reexamination Certificate

active

06677665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a dual-die integrated circuit package which can be used to pack two semiconductor dies in the same package unit.
2. Description of Related Art
A dual-die integrated circuit package is a type of integrated circuit package that contains two semiconductor dies therein so that a single unit of integrated circuit package can offer a doubled level of functionality or capacity than a single-die integrated circuit package. However, needless to say, a dual-die integrated circuit package would be greater in size than a single-die integrated circuit package. To allow a dual-die integrated circuit package to be nevertheless small in size, various packaging methods have been proposed. Some of these methods are briefly depicted in the following with reference to
FIGS. 6
,
7
,
8
,
9
, and
10
A-
10
C.
FIG. 6
is a schematic sectional diagram of a first conventional dual-die integrated circuit package structure. As shown, the package structure
1
includes a leadframe having a die pad
10
for mounting two semiconductor dies including a first semiconductor die
12
a
and a second semiconductor die
12
b
. The first semiconductor die
12
a
is adhered to the top side of the die pad
10
through silver paste
11
a,
while the second semiconductor die
12
b
is adhered to the bottom side of the same through silver paste
11
b.
Further, the first semiconductor die
12
a
is electrically coupled to the corresponding inner leads
140
of the leads
14
via a first set of bonding wires
13
a
; and in a similar manner, the second semiconductor die
12
b
is electrically coupled to the corresponding inner leads
140
of the leads
14
via a second set of bonding wires
13
b.
Finally, an encapsulant
15
is formed to encapsulate the first and second semiconductor dies
12
a
,
12
b
, the die pad
10
, the first and second sets of bonding wires
13
a
,
13
b
, and the inner leads
140
of the leadframe
14
, while exposing the outer leads
141
of the leads
14
to the outside for external connections.
During manufacture of the package structure
1
, it is required to perform the die-bonding process in two steps: a first step for mounting the first semiconductor die
12
a
on the upper side of the die pad
10
, and then a second step, which is performed by turning the entire die pad
10
upside down, for mounting the second semiconductor die
12
b
on the bottom side of the die pad
10
. As shown in
FIG. 7
, in this second step, the die pad
10
is positioned on a fixture
16
, and then a presser
17
is used to press down against the second semiconductor die
12
b
after it is mounted on the bottom side of the die pad
10
.
One drawback to the forgoing die-bonding process, however, is that since the functional surface of the first semiconductor die
12
a
, namely, the surface of the semiconductor die
12
a
on which electronic components and electric circuits are formed, comes in contact with the surface of the fixture
16
, the pressing down of the presser
17
would easily cause damage to the functional surface of the first semiconductor die
12
a
. Moreover, during the mounting of the first semiconductor die
12
a
onto the die pad
10
, since the die pad
10
has its bottom side come in contact with the platform of the die-bonding machine, it would easily cause contamination to the bottom side of the die pad
10
where the second semiconductor die
12
b
is to be mounted; and consequently, delamination would occur at the interface between the second semiconductor die
12
b
and the die pad
10
. Still moreover, since the die-bonding process requires the die pad
10
to be turned upside down for the mounting of the second semiconductor die
12
b
, it would be highly difficult to align the second semiconductor die
12
b
precisely to the first semiconductor die
12
a
; if misaligned, it would degrade the quality of the resulting integrated circuit package.
Further, the subsequent wire-bonding process is also required to be performed in two steps: a first step for bonding the first set of bonding wires
13
a
to the first semiconductor die
12
a
while positioning the first semiconductor die
12
a
on the top side of the die pad
10
, and then a second step, which is performed by turning the entire die pad
10
upside down, for bonding the second set of bonding wires
13
b
to the second semiconductor die
12
b.
One drawback to the foregoing wire-bonding process, however, is that when the die pad
10
is turned upside down subsequent to the wire bonding of the first set of bonding wires
13
a
, it would easily cause the first set of bonding wires
13
a
to come in contact with the fixture
16
, thus making the first set of bonding wires
13
a
easily deformed or damaged. Moreover, since the wire bonding of the first set of bonding wires
13
a
is carried out under a high-temperature condition and during which the bottom side
140
b
of the inner leads
140
comes in contact with the heating plate of the wire bonding machine, it would tend to cause the bottom side
140
b
of the inner leads
140
to be oxidized and contaminated, which would considerably affect the bonding quality between the second set of bonding wires
13
b
and the bottom side
140
b
of the inner leads
140
.
One solution to the foregoing drawbacks is the TAB (Tape Automated Bonding) method.
FIG. 8
shows a dual-die integrated circuit package which utilizes the TAB method to electrically connect the semiconductor die and the leads. As shown, the integrated circuit package
2
is used to pack two semiconductor dies including a first semiconductor die
24
a
and a second semiconductor die
24
b,
and includes a leadframe consisting of a die pad
20
and a plurality of leads
21
, each having an inner lead
210
and an outer lead
211
. The integrated circuit package
2
also includes a plurality of TAB leads
22
a,
22
b
for electrical connections of the semi-conductor dies
24
a
and the corresponding leads
21
. The top TAB leads
22
a
have a middle section attached by an insulative tape
23
a
on the top side of the die pad
20
, a first end electrically connected to the top surface
210
a
of the inner lead
210
, and a second end electrically connected to the bonding pads (not shown) on the first semiconductor die
24
a;
and in a similar manner, the bottom TAB leads
22
b
have a middle section attached by an insulative tape
23
b
on the bottom side of the die pad
20
, a first end electrically connected to the bottom surface
210
b
of the inner lead
210
, and a second end electrically connected to the bonding pads (not shown) on the second semiconductor die
24
b.
This arrangement allows the two semiconductor dies
24
a,
24
b
to be respectively electrically coupled via the TAB leads
22
a,
22
b
to the leads
21
.
The TAB technique can help eliminate the drawbacks of the dual-die integrated circuit package structure of FIG.
6
. However, since the use of the TAB technique requires the bonding pads on the semiconductor dies to be made from gold, it would significantly increase the manufacture cost. Moreover, it must be implemented by the use of a special machine called a gang bonding machine, which would further increase the manufacture cost since this type of machine is quite expensive as compared to conventional wire bonding machines. Further, the TAB technique requires complex processing steps so that the resulted integrated circuit packages are less reliable than the ones having conventional bonding wires.
As a solution to the drawbacks of the foregoing two dual-die integrated circuit package structures, U.S. Pat. No. 5,545,922 proposes a dual-die integrated circuit package having offset bonding wires, as illustrated in FIG.
9
. As shown, the integrated circuit package
3
is used to pack two semiconductor dies including a first semiconductor die
32
a
and a second semiconductor die
32
b.
The first semiconductor die
32
a
is adhered by silver paste
31
a
on the t

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