Dual delay mode pipelined logic simulator

Details Dual delay mode pipelined logic simulator Dual delay mode pipelined logic simulator

1986-06-25

1988-11-22

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 23, 364140, G06F 938, G06F 944

Patent

active

047870613

ABSTRACT:
Logic simulation is performed using special purpose hardware which operates in either one of two simulation modes. The machine allows detailed timing simulation where each device may be programmed with a delay time of zero, one, or multiple simulation time units. In addition, the machine supports zero and unit delay simulation in a high performance "unit delay" mode. The logic simulation function is partitioned into six sub-functions which are implemented in a single stage of a six-stage pipeline. The pipeline stages which implement the multi-unit delay time queue management may be switched to perform a different algorithm for unit delay simulation. The machine is able to perform extremely fast functional circuit testing and to perform detailed timing simulation without changing the circuit "netlist".

REFERENCES:
patent: 3932843 (1976-01-01), Trelut
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4313200 (1982-01-01), Nishiura
patent: 4342093 (1982-07-01), Miyoshi
patent: 4527249 (1985-07-01), Van Brunt
patent: 4584642 (1987-04-01), Hitchcock, Sr. et al.
patent: 4654851 (1987-03-01), Busby
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4656632 (1987-04-01), Jackson
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4725971 (1988-02-01), Doshi et al.
patent: 4725975 (1988-02-01), Sasaki
patent: 4751637 (1988-06-01), Catlin
M. Denneau, "Logic Processor for Logic Simulation Machine", IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982.
"Use of the Boeing Computer Simulator for Logic Design Confirmation and Failure Diagnostic Programs", A. W. Van Ausdal, Aeronautical Sci., 6/71.

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