Dual data rate memory strobe checker

Details Dual data rate memory strobe checker Dual data rate memory strobe checker

2006-10-23

2008-11-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

07457175

ABSTRACT:
A memory controller includes a gate circuit gating a data strobe signal from a memory device, a delay circuit delaying the data strobe signal from the gate circuit, a read buffer capturing values of a data signal from the memory device in response to the data strobe signal, a cumulative strobe counter incrementing a detected strobe count by the number of edges detected in the data strobe signal, and a control logic controlling the gate circuit and receiving the detected strobe count from the strobe counter. The control logic enables and disables the gate circuit after the start of a preamble and before the end of a postamble in the data strobe signal, respectively. When the memory controller is not expecting the data strobe signal from the memory device, the control logic compares the detected and the expected strobe counts and reports a strobe error when they do not match.

REFERENCES:
patent: 6215710 (2001-04-01), Han et al.
patent: 6940768 (2005-09-01), Dahlberg et al.
patent: 7345933 (2008-03-01), Telem et al.
patent: 7394707 (2008-07-01), Seto et al.

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