Dual damascene with a protective mask for via etching

Details Dual damascene with a protective mask for via etching Dual damascene with a protective mask for via etching

1995-06-07

1997-11-11

Dang, Thi

Fishing, trapping, and vermin destroying

437192, 437195, 437203, H01L 2128

Patent

active

056863543

ABSTRACT:
A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

REFERENCES:
patent: 4801350 (1989-01-01), Mattox et al.
patent: 5093279 (1992-03-01), Andreshak et al.
patent: 5227014 (1993-07-01), Crotti et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5294296 (1994-03-01), Yoon et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5444021 (1995-08-01), Chung et al.

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