Dual damascene trench formation to avoid low-K dielectric...

Details Dual damascene trench formation to avoid low-K dielectric... Dual damascene trench formation to avoid low-K dielectric...

2007-01-30

2007-01-30

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S637000, C438S780000, C257SE21579, C257SE21024

Reexamination Certificate

active

10882058

ABSTRACT:
A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

REFERENCES:
patent: 6924221 (2005-08-01), Shen
patent: 2004/0002210 (2004-01-01), Goldberg et al.
patent: 2004/0018721 (2004-01-01), Kim et al.
patent: 2004/0175934 (2004-09-01), America et al.
patent: 2005/0106856 (2005-05-01), Chen et al.

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