Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-27
2002-11-19
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S762000
Reexamination Certificate
active
06483142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an integrated circuit including capacitors. In particular, the present invention relates to a damascene structure of capacitors having uniform thickness of insulators.
2. Description of the Related Art
Capacitors are integrated in various integrated circuits. For example, capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. These capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuits and so on.
A conventional method of manufacturing a semiconductor apparatus including a capacitor
20
that is formed of metal-insulator-metal layers is described with reference to FIGS.
1
A~
1
D. As shown in
FIG. 1A
, an aluminum layer is deposited on an insulator
12
which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires
14
a
and
14
b.
As shown in
FIG. 1B
, an insulator
16
with a tungsten plug
18
(hereafter are referred to W-plug) for connecting the aluminum wire
14
a
and to-be-formed capacitor is formed on the aluminum wires
14
a
and
14
b
and the insulator
12
. As shown in
FIG. 1C
, a first conductive plate
21
, an insulator
22
and a second conductive plate
23
are sequentially deposited on the insulator
16
and the W-plug
18
, and then patterned by masking and etching to constitute a capacitor
20
. The first conductive plate
21
, which is used as the bottom electrode, is connected with the aluminum wire
14
a
through the W-plug
18
. Another insulator
26
is deposited on the insulator
16
and the capacitor
20
. The insulators
16
and
26
are patterned to form W-plug
28
a
and W-plug
28
b.
As shown in
FIG. 1D
, an aluminum layer (not shown) is deposited on the insulator
26
and the W-plugs
28
a
and
28
b.
The aluminum layer is then patterned by masking and etching to form wires
34
a
and
34
b.
The aluminum wire
34
a
is connected with the second conductive plate
23
through the W-plug
28
a.
The aluminum wire
34
b
is connected with the aluminum wire
14
b
through the W-plug
28
b.
The above-mentioned method for integrating the capacitor
20
into the integrated circuits is not cost-effective enough because it requires several masking steps to form the capacitor
20
.
With the enhancements of the integration and the highly demanding speed of data transmission, the aluminum interconnections cannot satisfy these trends. Copper (Cu) has high electric conductivity to reduce RC delay and can be substituted for the aluminum as conducting wires. Using copper as the conducting wires need additional processes, that is, damascene processes. During the etching process using chlorine plasma, the boiling point of copper chloride (CuCl
2
) produced by copper and chlorine can reach temperature as high as 1500° C., so copper cannot be patterned by conventional etching process.
A thin-film capacitor formed by combining with the Cu damascene processes is disclosed in U.S. Pat. No. 6,180,976 B1. In the '976 B1 patent, the bottom electrode of the thin-film capacitor is also formed by the damascene process. The '976 B1 patent has advantage of saving a masking step. However, a chemical mechanical polishing process is required to remove the undesirable metal material to form the bottom electrode. The dishing phenomenon is likely to occur on the bottom electrode and result in uneven surface. Therefore, the thickness of the insulator can not be controlled to be unvaried and uniform, thereby to stabilize the electrical properties of the capacitors.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method of forming a damascene structure having capacitors.
It is another object of the present invention to provide a method of forming a damascene structure having capacitors, which uses relatively fewer masking steps.
The present invention provides a dual damascene structure having capacitors. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first insulator and the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A bottom electrode is located on the third insulator and the first Cu plug, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the bottom electrode and the conducting wire. An upper electrode is located on the fourth insulator, and corresponding to the bottom electrode. A fifth insulator with a flat surface is located on the upper electrode, the fourth insulator and the third insulator. A first dual damascene structure and a second dual damascene structure are located in the fifth insulator and the fourth insulator, the first dual damascene structure comprising a third Cu wire and a third Cu plug, the second dual damascene structure comprising a fourth Cu wire and a fourth Cu plug, wherein the upper electrode is connected to the third Cu wire through the third Cu plug, and the conducting wire is connected to the fourth Cu wire through the fourth Cu plug. A second sealing layer is located on the third and fourth Cu wires and the fifth insulator.
REFERENCES:
patent: 5808855 (1998-09-01), Chan et al.
patent: 6159839 (2000-12-01), Jeng et al.
patent: 6180976 (2001-01-01), Roy
Hsue Chen-Chiu
Lee Shyh-Dar
Silicon Integrated Systems Corp.
Tsai Jey
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