Dual damascene structure formed of low-k dielectric materials

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S622000, C438S680000, C438S624000, C438S637000, C438S634000, C438S638000, C438S708000, C438S672000, C438S675000, C438S626000, C438S636000

Reexamination Certificate

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07015133

ABSTRACT:
A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.

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A. Kajita, et al., Highly Reliable Cu/low-k Dual Damascene Interconnect Technology with Hybrid (PAE/SiOC) Dialectrics for 65 nm-node High Performance eDRAM, Proceedings of the IEEE 2003 International Interconnect Technology Conference, Jun. 2003.

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