Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-05
2003-05-13
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C148S033200, C216S038000, C216S088000, C257S752000, C438S692000
Reexamination Certificate
active
06562725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming dual damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for forming low dielectric constant dual damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants in a range of from about 1.5 to less than about 4.0. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 3.5 to about 8.0. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers formed of dielectric materials having comparatively low dielectric constants provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, such damascene methods often damage the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated damage to the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties in the art of microelectronic fabrication.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within: (1) Zhao et al., in U.S. Pat. No. 6,100,184 (a dual damascene method for forming a copper containing contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed of a comparatively low dielectric constant dielectric material to contact a copper containing conductor layer formed thereunder while employing a conductor barrier/etch stop layer formed selectively passivating only the top surface of the copper containing conductor layer formed thereunder); (2) Grill et al., in U.S. Pat. No. 6,140,226 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant dielectric material while employing a sidewall liner layer for purposes of protecting from lateral etching a sidewall of the trench when forming contiguous therewith the via while employing the dual damascene method); and (3) Huang, in U.S. Pat. No. 6,177,364 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed of a comparatively low dielectric constant fluorosilicate glass (FSG) dielectric material while employing a hydrogen-nitrogen plasma treatment for purposes of passivating a sidewall surface of the dielectric layer within the corresponding trench contiguous with the corresponding via prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer).
Desirable in the art of microelectronic fabrication are additional damascene methods and materials which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated damage to the microelectronic dielectric layers.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is formed with attenuated damage to the microelectronic dielectric layer.
A third object of the present invention is to provide a damascene method in accord with the first object
Hsieh Ching-Hua
Shue Shau-Lin
Tsai Ming-Hsing
Yu Chen-Hua
Powell William A.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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