Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-08
2007-05-08
Kebede, Brook (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S639000, C257SE21579
Reexamination Certificate
active
11162154
ABSTRACT:
A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.
REFERENCES:
patent: 2003/0199169 (2003-10-01), Jun et al.
patent: 2004/0166666 (2004-08-01), Usami
patent: 2004/0219796 (2004-11-01), Wu
Huang Jen-Ren
Lin Miao-Chun
Weng Cheng-Ming
Jiang Chyun IP Office
Kebede Brook
United Microelectronics Corp.
LandOfFree
Dual damascene structure and fabrication thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual damascene structure and fabrication thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene structure and fabrication thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3764958