Dual-damascene process with porous low-K dielectric material

Details Dual-damascene process with porous low-K dielectric material Dual-damascene process with porous low-K dielectric material

2001-05-17

2002-04-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000, C438S687000

Reexamination Certificate

active

06365506

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor device having a conductive interconnect, and more particularly, to a dual damascene process for conductive interconnects using a porous low-k dielectric material.
2. Description of the Prior Art
The trend of semiconductor processing technique is toward scaling down the dimensions of semiconductor devices such as integrated circuits (IC). The scaling-down of IC dimensions, however, requires an increase of the number of interconnect levels and interconnect wiring with minimum pitch. As the IC is scaled down, metallization, which interconnects devices on the IC, is also scaled down. It has been well recognized in the semiconductor industry that damascene process and its twin, dual-damascene process, are promising technologies for fabricating metal lines and interconnects in IC. Furthermore, the dual damascene process will be broadly applied in the fabrication process of ultra large semiconductor integration (ULSI) interconnects beyond 0.18 um technology. The greatest advantage of the dual damascene process is that the metal lines are not etched, but deposited in trench lines and via holes etched away with one etching step or a series of etching steps within the dielectric layer, and then excess metal is removed by polish. In principle, there are two standard modes of the dual damascene techniques, namely, via-first and trench-first.
Referring to
FIG. 1
, ICs typically include multi-level metallization. A first metal line
11
is contained within a first trench line
13
etched in a first trench insulating layer
15
. A second metal line
12
is contained within a second trench line
14
etched in a second trench insulating layer
16
. The first metal line
11
is on a first metallization level on the IC, and the second metal line
12
is on a second metallization level on the IC. A via interconnects the metal lines
11
and
12
on the two different metallization levels. A via plug
17
is comprised of a conductive material and is deposited within a via hole
18
etched in a via insulating layer
19
. The insulating layers
15
,
16
and
19
are comprised of any insulating material such as oxide as is known to one of ordinary skill in the art.
Silicon dioxide with a dielectric constant (k) around 3.9 to 4.1 has been widely used in the semiconductor industry to insulate individual wires and circuits. With the increased integration density, the use of SiO
2
with constant thickness is more and more difficult and costly. Advanced materials are expected to provide a low-k material with k value below 3, and even to develop porous materials with ultralow-k under 2.5. Ultralow-k dielectric materials, such as XLK of Dow Corning Corporation, are porous and less robust. With such a porous material, the via-first and trench-next dual damascene technique can not be processed because the subsequent resist or BARC for gap-filling will be absorbed into the pores or voids of the ultralow-k dielectric materials.
Referring to
FIG. 2A
, a prior art dual damascene process with ultralow-k dielectric is disclosed, including a step of depositing a bottom nitride layer
22
on a first metal layer
21
. A via insulating layer of ultralow-k dielectric material
23
is deposited on the bottom nitride layer
22
. A via masking layer
24
is deposited on the via insulating layer
23
. The via masking layer
24
is etched to have a via pattern for defining a via hole in the via insulating layer
23
. The via masking layer
24
typically is comprised of a hard mask material such as nitride.
A trench insulating layer of ultralow-k dielectric material
25
is deposited on the via masking layer
24
. A trench masking layer
26
is deposited on the trench insulating layer
25
. The trench masking layer
26
is comprised of a hard mask material such as nitride. Then, a trench pattern is etched into the trench masking layer
26
using a photoresist layer
27
, as is known to one of ordinary skill in the art of IC fabrication so that the size, shape and location of a trench line
28
are defined.
Referring to
FIG. 2B
, the photoresist layer
27
is removed before the dual damascene process for forming the trench line
28
and a via hole
29
. Referring to
FIG. 2C
, the trench line
28
and the via hole
29
is etched by the dual damascene etch.
Referring to
FIG. 2D
, any exposed masking layers
24
and
26
(and the nitride layer
22
) are etched away before the via hole
29
and the trench line
28
are filled with conductive material. The trench masking layer
26
is aligned with the via masking layer
24
such that the trench line
28
, defined by the trench pattern, is contiguous with the via hole
29
, defined by the via pattern. Thus, the first conductive material filled within the via hole
29
forms a conductive path with the second conductive layer filled within the trench line
28
, as illustrated in FIG.
1
.
Those of ordinary skill in the art know that the first conductive material filled within the via hole
29
and the second conductive material filled within the trench line
28
may be the same type of conductive material, or alternatively, different conductive material. They may be aluminum or copper, or any other conductive material known to one of ordinary skill in the art to be used for IC fabrication.
With the prior art dual damascene etch of
FIG. 2
, because the insulting layers of ultralow-k dielectric materials
23
and
25
are deposited respectively, the process appears complicated. Furthermore, the via masking layer
24
used as an etching stop in the dual damascene etch has a high k value. Such a masking layer when in cooperation with a ultralow-k dielectric will significantly increase the capacitance between the first metal layer
21
and the second metal layer filled within the trench line
28
, and hence, on-chip speed is decreased.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a dual damascene process. In the dual damascene process according to the invention, the disadvantages of the conventional process are improved upon.
Another object of the invention is to provide integration of porous low-k dielectric materials with the dual damascene process to prevent from direct contact with the photoresist which is deposited thereon subsequently and generally contains poisonous composition such as moisture for low-k dielectrics.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a dual damascene process with porous low-k dielectric. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.


REFERENCES:
patent: 6071809 (2000-06-01), Ahao
patent: 6184128 (2001-02-01), Wang et al.
patent: 6245663 (2001-06-01), Zhao et al.
patent: 2001/0002331 (2001-05-01), Miyata

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