Dual damascene process using single photoresist process

Details Dual damascene process using single photoresist process Dual damascene process using single photoresist process

1997-10-14

1999-03-02

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438638, 438700, H01L 2144

Patent

active

058770755

ABSTRACT:
A simplified method is disclosed for forming dual damascene patterns using a single photoresist process. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a "clear-field" mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. The vertical hole is transferred into the middle layer of the underlying composite layer by dry etching. Twine pattern which is next formed in the same photoresist layer is transferred into the top layer of the composite layer while at the same time the hole pattern is transferred to the bottom layer. Having thus formed the vertical hole interconnect and line trench into the insulation layer, metal is deposited into the dual damascene pattern. Any excess metal on the surface of the insulating layer is then removed by any number of ways including chemical-mechanical polishing, thereby planarizing the surface and readying it for the next semiconductor process.

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