Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-30
2004-03-09
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000
Reexamination Certificate
active
06703304
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
FIELD OF THE INVENTION
The present specification relates generally to a process of forming a trench for an integrated circuit and, more specifically, to a dual damascene process of forming a trench for an integrated circuit (IC). Even more specifically, the present specification relates to a dual damascene process that uses a self-assembled monolayer and a spacer.
BACKGROUND OF THE INVENTION
The increased demand for higher performance integrated circuit (IC) devices has required the density of metallization lines to be increased and, in addition, has required the use of stacked layers to be increased. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but are also conducive to subsequent CMP (chemical mechanical polishing) processing. CMP is necessary to ensure that a subject layer is flat (surface uniformity) and planar enough to serve as a bottom layer for an additional layer.
As interconnection line widths shrink, the challenges of etching materials using photoresist-as-mask techniques have become increasingly difficult. A major cause of the difficulty is the large aspect ratios involved. The aspect ratio is the ratio of the depth of a feature being etched to the width of the feature (D/W) (or height-to-width in cross-section).
One method of forming a trench is a method known as a damascene process, which comprises forming a trench by masking and etching techniques and subsequent filling of the trench with the desired conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advanced semiconductor devices. A dual damascene process is a two-step sequential mask/etch process to form a two-level structure, such as a via, connected to a metal line above the via.
Conventional dual damascene processing technology entails depositing a triple layer sandwich consisting of a thick layer of an insulative material, an etch stop material having a high etch selectivity to the insulative layer, and a second thick layer of an insulative material. The two level structure is formed by masking and etching through the top layer of insulative material stopping on the layer of etch stop material, etching the etch stop material only, then performing a second masking and etching process in the top layer of insulative material only. The second mask and etch provides a larger trough than the first mask and etch with the second masking being an oversize masking.
The demand for increased density has required an increase in the aspect ratio of the photolithographic processes. However, the current dual damascene process has several problems that prevent the further increase of the aspect ratio. The lithography systems being used to expose the photoresist in the resist-as-mask process are limited by the wavelength of light used, the compositions of the photoresist, and the lithographic techniques employed.
Accordingly, an improved method of fabricating a trench for an integrated circuit is needed. Further, a method of fabricating a trench for an integrated circuit having a smaller width than available with conventional dual damascene processes is needed. Further still, what is needed is a method of fabricating a trench for an integrated circuit having a width which is controllable to dimensions not possible using conventional dual damascene processes. Further yet, what is needed is a method of forming interconnect lines for an IC using less critical masks than in conventional dual damascene processes. Also, what is needed is a method of fabricating a trench having a high aspect ratio. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
SUMMARY OF THE INVENTION
According to an exemplary embodiment, a method of fabricating a trench for an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers. The method further includes forming a first self-assembled monolayer on the layer of material and etching the first self-assembled monolayer to form an aperture in the layer of material. The method further includes etching the first insulative layer through the first aperture. A top surface of the second insulative layer is exposed. The method further includes depositing a spacer layer over the layer of material. A portion of the spacer layer masks a portion of the top surface of the second insulative layer. The method further includes etching the second insulative layer.
According to another exemplary embodiment, a method of fabricating a trench for an integrated circuit includes providing first and second insulative layers over a semiconductor substrate and fabricating a layer of material having a topographical transition region over the first insulative layer. The method further includes forming a self-assembled molecular layer over the layer of material. The self-assembled molecular layer has a region of etch selectivity at the topographical transition region. The method further includes etching the self-assembled molecular layer at the region of etch selectivity to form an aperture in the layer of material and etching the first insulative layer to form a first portion of the trench. The method further includes depositing a spacer layer over the layer of material and etching the spacer layer to expose a top surface of the second insulative layer. The method further includes etching the second insulative layer to form a second portion of the trench.
According to yet another exemplary embodiment, an integrated circuit has a trench. The trench is fabricated by providing first and second layers of material over a semiconductor substrate and providing a layer of material over the insulative layers. The trench is further fabricated by forming a first self-assembled monolayer on the layer of material and etching the first self-assembled monolayer to form an aperture in the layer of material. The trench is further fabricated by etching the first insulative layer through the first aperture. A top surface of the second insulative layer is exposed. The trench is further fabricated by depositing a spacer layer over the layer of material. A portion of the spacer layer masks a portion of the top surface of the second insulative layer. The second insulative layer is etched.
REFERENCES:
patent: 4728591 (1988-03-01), Clark et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5079600 (1992-01-01), Schnur et al.
patent: 5512131 (1996-04-01), Kumar et al.
patent: 5512328 (1996-04-01), Yoshimura et al.
patent: 5514501 (1996-05-01), Tarlov
patent: 5618760 (1997-04-01), Soh et al.
patent: 5725788 (1998-03-01), Maracas et al.
patent: 5727977 (1998-03-01), Maracas et al.
patent: 5751018 (1998-05-01), Alivisatos et al.
patent: 5885753 (1999-03-01), Crooks et al.
patent: 5922214 (1999-07-01), Liu et al.
patent: 5981350 (1999-11-01), Geusic et al.
patent: 6048623 (2000-04-01), Everhart et al.
patent: 6071812 (2000-06-01), Hsu et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6114099 (2000-09-01), Liu et al.
patent: 6174775 (2001-01-01), Liaw
patent: 6174804 (2001-01-01), Hsu
patent: 6184126 (2001-02-01), Lee et al.
patent: 6187657 (2001-02-01), Xiang
patent: 6225658 (2001-05-01), Watanabe
patent: 6238982 (2001-05-01), Krivokapic et al.
patent: 6262456 (2001-07-01), Yu et al.
patent: 6297169 (2001-10-01), Mangat et al.
patent: 6365466 (2002-04-01), Krivokapic
patent: 6380101 (2002-04-01), Breen et al.
patent: 6413587 (2002-07-01), Hawker et al.
patent: 6534399 (2003-03-01), Krivokapic
patent: 2001/0039114 (2001-11-01), Nakamura
patent: 325465 (2002-02-01), None
Lu et al., Ultrathin resist films patterning using a synchrotron radiation lithography system, Sep. 7, 1996, pp. 103-105.
Huang et al., Photopatterning of S
Foley & Lardner
Perkins Pamela E
Zarabian Amir
LandOfFree
Dual damascene process using self-assembled monolayer and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual damascene process using self-assembled monolayer and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process using self-assembled monolayer and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3248483