Dual damascene process using sacrificial spin-on materials

Details Dual damascene process using sacrificial spin-on materials Dual damascene process using sacrificial spin-on materials

2000-03-22

2002-07-23

Utech, Benjamin L. (Department: 1765)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S759000, C257S760000, C257S774000

Reexamination Certificate

active

06424039

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a dual damascene process for forming a contact hole for an integrated circuit (IC) and more particularly to a dual damascene process that uses a sacrificial layer of spin-on material for protecting the contact hole profile during the damascene etch process.
2. Description of the Related Art
A conventional dual damascene process is described in Licata et al., “Dual Damascene Al Wiring for 256M DRAM,” Proceedings of the 12th International VLSI Multilevel Interconection Conference, edited by T. E. Wade (VMIC, Tampa), pp. 596-602 (1995).
FIGS. 1A-1F
illustrate the steps of the conventional dual damascene process.
FIG. 1A
illustrates an oxide layer
20
disposed on top of a semiconductor substrate
10
. A layer of photoresist
30
is spin coated on top of the oxide layer
20
, exposed through a mask (not shown) containing a contact hole pattern, and developed. An etch opening
31
is thus formed. Using the remaining photoresist as an etch mask, the oxide layer
20
is then etched to form a contact hole
32
and the remaining photoresist is then removed producing the structure shown in FIG.
1
B.
Next, a layer of photoresist
33
is applied a second time (FIG.
1
C). The photoresist
33
is then exposed through a mask (not shown) and developed to form an etch opening
34
(FIG.
1
D). Using the remaining photoresist as an etch mask, the oxide layer
20
is etched to form a wiring trough
35
as shown in FIG.
1
E. This etch step is known as a damascene etch step. The remaining photoresist is removed and the contact hole
32
and the wiring trough
35
are filled with metal
36
.
The above-described process is difficult to control for three reasons.
First, the reflectivity from the topography substrate makes the width of the etch opening
34
in the photoresist
33
difficult to control.
Second, as feature sizes have become smaller, the aspect ratio (height/width) of the contact hole
32
has increased. At high aspect ratios, it is difficult for the photoresist
33
to completely flow into and fill the contact hole
32
. If the contact hole is not completely filled, there is a possibility that the photoresist
33
disposed within the contact hole
32
may partially or even completely develop away and provide little or no protection for the contact hole profile during the subsequent damascene etch step.
Third, the thickness of the photoresist
33
over the topography substrate varies signficantly, and so the exposure depth of the photoresist
33
is difficult to control. This is likely to cause an over-development of the photoresist
33
disposed within the contact hole
32
and possibly erode the contact hole profile during the subsequent damascene etch step.
SUMMARY OF THE INVENTION
An object of this invention is to provide a dual damascene process that produces more consistent results by employing an improved process control.
Another object of this invention is to provide a dual damascene process for forming a semiconductor structure with improved damascene etch profiles.
Still another object of this invention is to provide for use in a dual damascene process a semiconductor structure having a sacrificial layer of anti-reflective coating material.
The above and other objects of the invention are accomplished by a dual damascene process including the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough.
The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough. The anti-reflective coating material can be non-photosensitive, and is termed a “sacrificial layer” because it is added and then “sacrificed” (i.e., removed) for the, purpose of performing an interim function in the dual damascene process.
The dual damascene process according to the invention employs a semiconductor structure including a substrate, an oxide layer disposed above the substrate, and a layer of anti-reflective coating material disposed on top of the oxide layer. The oxide layer has a contact hole which is filled by the anti-reflective coating material when the anti-reflective coating material is disposed on top of the oxide layer. A photoresist formed to have a wiring trough pattern is disposed on top of the layer of the anti-reflective coating material. The wiring trough pattern defines an opening which is aligned with the contact hole and which has a width larger than that of the contact hole. The photoresist is used as a mask during the damascene etching step that forms the wiring trough in the oxide layer in alignment with the contact hole.
Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.


REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 5066615 (1991-11-01), Brady et al.
patent: 5100503 (1992-03-01), Allman et al.
patent: 5110697 (1992-05-01), Lame, III et al.
patent: 5219788 (1993-06-01), Abernathey et al.
patent: 5264076 (1993-11-01), Cuthbert et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5401613 (1995-03-01), Brewer et al.
patent: 5539080 (1996-07-01), Hogan et al.
patent: 5573634 (1996-11-01), Ham
patent: 5635423 (1997-06-01), Huang et al.
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5759911 (1998-06-01), Cronin et al.
patent: 5910018 (1999-06-01), Jang
patent: 6074959 (2000-06-01), Wang et al.
Licata et al., “Dual Damascene AI Wiring For 256M Dram” VMIC Conference pp. 596-602 (1995).

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