Dual damascene process using metal hard mask

Details Dual damascene process using metal hard mask Dual damascene process using metal hard mask

2001-07-24

2004-02-24

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S311000, C430S312000, C430S314000, C430S316000, C430S317000, C430S318000, C216S041000, C216S051000, C438S622000, C438S634000, C438S637000, C438S638000, C438S734000, C438S737000, C438S740000, C438S742000

Reexamination Certificate

active

06696222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual damascene process and, more particularly, to a dual damascene process using at least one metal hard mask.
2. Description of the Related Art
High-density integrated circuits, such as very large scale integration (VLSI) circuits, are typically formed with multiple metal interconnects to serve as three-dimensional wiring line structures. The purpose of multiple interconnects is to properly link the densely packed devices together. With increasing levels of integration, a parasitic capacitance effect between the metal interconnects, which leads to RC delay and cross talk, increases correspondingly. Therefore, in order to reduce the parasitic capacitance for increasing the speed of conduction between the metal interconnections, a type of low-k organic dielectric material is commonly employed to form an inter-layer dielectric (ILD) layer. However, there are technical problems regarding the use of low-k organic dielectric materials for the ILD layers.
FIGS. 1A
to
1
C depict cross-sectional diagrams of the formation of a via hole between metal interconnects using conventional technique. As shown in
FIG. 1A
, a semiconductor substrate
10
has a metal wire structure
12
, a low-k dielectric layer
14
formed over the exposed substrate
10
and the metal wire structure
12
, an oxide hard mask
16
deposited over the low-k dielectric layer
14
, and a photoresist layer
18
patterned on the oxide hard mask
16
. Using the photoresist layer
18
as a mask, the oxide hard mask
16
is etched to form an opening above the metal wire structure
12
. Then, as shown in FIG.
1
B. etching is continued to form a via hole
19
in the low-k dielectric layer
14
. The via hole
19
with steep sidewalls
15
exposes the metal wire structure
12
. Finally, the photoresist layer
18
is removed by oxygen plasma process. However, the low-k dielectric layer
14
of carbon-containing organic polymer has properties very similar to the photoresist layer
18
, and the low-k dielectric layer
14
, has very low resistance against oxygen plasma etching. Therefore, as shown in
FIG. 1C
, a portion of the exposed sidewalls
15
will be removed during the oxygen plasma process, resulting in recess cavities
15
a
forming on the sidewalls
15
. Also, if a BARC is used under the photoresist layer
18
, the etch profile of the via hole
19
will be more difficult to control. In addition, since the oxygen plasma easily poisons low-k organic materials, only SiO
2
based materials such as FSG, USG, BLACK DIAMON, CORAL, AURORA, and FLOWFILL are suitable for making the low-k dielectric layer.
14
. Thus, the use of low-k organic materials is limited in conventional technique.
Seeking to solve the aforementioned problems, U.S. Pat. No. 6,159,661 discloses a damascene process including the formation of an additional cap layer, preferably of silicon oxynitride (SiON), over the oxide hard mask. The cap layer is able to protect the low-k dielectric layer from oxygen plasma process when stripping the photoresist layer. However, when patterning the cap layer, the problem of tuning a high etching-selectivity between the cap layer and the oxide hard mask is encountered. Further, only low-k organic materials can be applied to the formation of the ILD layers.
Thus, a dual damascene process using dual hard masks, in which at least the hard mask contacting the low-k dielectric layer is of metallic materials, is desired to solve the aforementioned problems
SUMMARY OF THE INVENTION
The present invention is a dual damascene process with dual hard masks, in which at least the hard mask contact the low-k dielectric layer is of metallic materials.
The dual damascene process is provided on a semiconductor substrate, which has a conductive structure, a dielectric separation layer covering the conductive structure, and a low-k dielectric layer over the dielectric separation layer. The conductive structure is preferably copper. The low-k dielectric layer may be of organic polymer formed by a spin-on coating process, and alternatively may be SiO2-based materials formed by chemical vapor deposition (CVD). In another preferred embodiment, a patterned etch stop layer is additionally provided in the low-k dielectric layer serving as a hard mask in the subsequent process of forming a via hole and serving as an etching endpoint in the subsequent process of forming a trench.
A first hard mask of metallic material is formed on the low-k dielectric layer, and then a second hard mask is formed on the first hard mask. The second hard mask may be metallic or dielectric material. Next, using photolithography and etching, a first opening is formed in the second hard mask over the conductive structure, and then a second opening is formed in the first hard mask under the first opening. The diameter of the first opening is larger then the second opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed until the dielectric separation layer is exposed, thereby forming a via hole in the low-k dielectric layer. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and the exposed low-k dielectric layer is then removed to reach a predetermined depth. As a result, a trench is formed over the via hole, and the trench and the via hole serve as a dual damascene opening.
Accordingly, it is a principle object of the invention to provide dual metal hard masks for preventing oxygen plasma from making contact the low-k dielectric layer when a photoresist layer is removed.
It is another object of the invention to increase the gap-filling capacity of the subsequently deposited conductive layer in the dual damascene opening.
Yet another object of the invention is to provide low-k organic materials in the formation of the low-k dielectric layer.
It is a further object of the invention to reduce RC delay and cross talk, therefore allowing chip size to be scaled down to the next generation.
Still another object of the invention is to provide the dual hard masks as an anti-reflection coating (ARC) in subsequent deep ultra violet (DUV) photolithographic operations.
Another object of the invention is to lower the production cost and simplify the dual damascene process.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.


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patent: 6071809 (2000-06-01), Zhao
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patent: 6114250 (2000-09-01), Ellingboe et al.
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patent: 2003/0008490 (2003-01-01), Xing et al.
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