Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-10-28
2000-08-01
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438619, 438723, 438724, 438738, 438743, 438744, 257758, H01L 214763, H01L 2348, H01L 2940
Patent
active
060966335
ABSTRACT:
A method of forming local interconnects uses a dual damascene process. The process comprises the steps of first providing a substrate, and then forming a first insulating layer over the substrate. Then, a pillar-shaped second insulating layer is formed over the first insulating layer. Thereafter, a first conductive layer is formed over the first insulating layer and the second insulating layer, and then a third insulating layer is formed over the first conductive layer. In the subsequent step, a portion of the third insulating layer and the first conductive layer is polished away using a chemical-mechanical polishing operation, stopping at the surface of the second insulating layer. Next, a fourth insulating layer is formed over the third insulating layer, the second insulating layer and the first conductive layer, wherein the fourth insulating layer and the second insulating layer are made from the same material. Then, the fourth insulating layer is etched to remove the fourth insulating layer above the second insulating layer and the entire second insulating layer, thereby forming a self-aligning via. Subsequently, a second conductive material is deposited over the substrate and into the self-aligning via to form a second conductive layer. Finally, a chemical-mechanical polishing method is again used to polish away a portion of the second conductive layer, stopping at the upper surface of the fourth insulating layer.
REFERENCES:
patent: 3539705 (1970-11-01), Nathanson et al.
patent: 5567982 (1996-10-01), Bartelink
patent: 5933761 (1999-08-01), Lee
patent: 5949143 (1999-09-01), Bang
Nguyen Ha Tran
Niebling John F.
United Microelectronics Corp.
LandOfFree
Dual damascene process for forming local interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual damascene process for forming local interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process for forming local interconnect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-663350