Dual damascene process for forming a multi-layer low-k...

Details Dual damascene process for forming a multi-layer low-k... Dual damascene process for forming a multi-layer low-k...

2007-10-23

2007-10-23

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S675000, C438S687000, C257SE21579

Reexamination Certificate

active

11063552

ABSTRACT:
In a dual damascene process for forming a multi-layer low-k dielectric interconnect, the formation of each layer of interconnect comprises deposition of a first low-k dielectric layer, etching of the first low-k dielectric layer to form two dual damascene vias, formation of two Cu conductor plugs enclosed with barrier layers in the two dual damascene vias, etching of the first low-k dielectric layer between the two dual damascene vias to form a trench, and spin-on of a second low-k dielectric layer filled in the trench. The spin-on low-k dielectric layer is selected to have a dielectric constant smaller than that of the first low-k dielectric layer to reduce the equivalent dielectric constant in the layer of interconnect.

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