Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-17
2001-04-03
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S639000
Reexamination Certificate
active
06211069
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a small diameter opening, in an insulator layer, used to accommodate a dual damascene metal structure.
(2) Description of Prior Art
The use of damascene, or dual damascene metal structures, have allowed the semiconductor industry to reduce process complexity and cost. The ability to fabricate an overlying, wide diameter, metal interconnect structure, and an underlying, narrow diameter, metal via structure, using only a single metal deposition, and patterning procedure, has allowed the cost and process complexity objectives to be realized. A dual damascene opening, formed in a composite insulator layer, comprised of a wide diameter opening, and of an underlying, narrower diameter opening, is used to accommodate the subsequent dual damascene metal structure. However as demands for sub-micron devices increase, the photolithographic limits, in regards to the critical dimension of the narrow diameter opening, of the dual damascene opening, becomes critical.
This invention will teach a process in which a dual damascene opening, in a composite insulator layer, is used to accommodate a subsequent dual damascene metal structure, comprised of an overlying, wide diameter, metal interconnect structure, and an underlying, narrow diameter, metal via structure. However to further decrease the diameter of the subsequent metal via structure, in an effort to increase device density, a novel spacer technology is employed. The use of insulator spacers, formed on the exposed sides of the dual damascene opening, result in a narrowing of the narrow diameter opening, thus allowing metal via structures to be realized, that are narrower in diameter than counterparts formed in openings achieved using only photolithographic patterning procedures. In addition this invention allows the photolithographic process window, for either critical dimension, or overlay, to be increased, thus avoiding possible image, or overlay problems, encountered with the use of more aggressive groundrules. The use of the spacers reduce the diameter of the openings, to a level only achievable using riskier photolithographic procedures. Prior art, such as Irinoda, in U.S. Pat. No. 5,726,499, describes a process in which spacers are used as part of an etch mask, to decrease the diameter of an etch mask opening, used to define an underlying, smaller diameter opening. In contrast, this invention does not use the spacer as an etch mask, but fabricates the spacer on the walls of a formed, small diameter opening, which was achieved using only conventional photolithographic and dry etching procedures, followed by the narrowing of the narrow diameter opening, via formation of the insulator spacer.
SUMMARY OF THE INVENTION
It is an object of this invention to create a dual damascene metal structure, in an opening formed in a composite insulator layer.
It is another object of this invention to form an initial dual damascene opening, in a composite insulator layer, using photolithographic and dry etching procedures, with the dual damascene opening, comprised of an overlying, wide diameter opening, and of an underlying, narrow diameter opening.
It is still another object of this invention to form insulator spacers on the sides of the initial dual damascene opening, to create a final dual damascene opening, now featuring a smaller diameter than the initial dual damascene opening.
It is still yet another object of this invention to allow a larger photolithographic process window, in terms of critical dimension and overlay, to be used to create the initial dual damascene opening, in a composite insulator layer, followed by the creation of the smaller diameter, final dual damascene opening, obtained via creation of the insulator spacers.
In accordance with the present invention, a method of creating a final dual damascene opening, in a composite insulator layer, featuring a reduction of the diameter of an initial dual damascene opening, via the creation of insulator spacers, on the sides of the initial dual damascene opening, has been developed. A composite insulator layer, comprised of an underlying silicon oxide layer, a silicon nitride stop layer, and an overlaying silicon oxide layer, is deposited. Conventional photolithographic and dry etching procedures, are employed to create an initial dual damascene opening, in the composite insulator layer, comprised of a overlying, wide diameter opening, and an underlying, narrow diameter opening. An insulator layer is next deposited, then subjected to an anisotropic reactive ion etching procedure, to create insulator spacers on the sides of the initial dual damascene opening, resulting in a final dual damascene opening, featuring smaller diameter openings, than previously exhibited with the initial dual damascene opening. Deposition of a barrier layer, and a metal layer, followed by removal of unwanted regions of metal, and of barrier layer, result in a dual damascene metal structure, located in the final dual damascene opening, in the composite insulator layer.
REFERENCES:
patent: 5604156 (1997-02-01), Chung et al.
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 5726499 (1998-03-01), Irinoda
patent: 5741626 (1998-04-01), Jain et al.
patent: 5753967 (1998-05-01), Lin
patent: 5795823 (1998-08-01), Avanzino et al.
patent: 5814527 (1998-09-01), Wolstenholme et al.
patent: 6010962 (2000-01-01), Liu et al.
Hu Chu-Wei
Shiue Ruey Yun
Weng Jiue Wen
Ackerman Stephen B.
Gurley Lynne A.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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