Dual damascene process and structure with dielectric barrier lay

Details Dual damascene process and structure with dielectric barrier lay Dual damascene process and structure with dielectric barrier lay

1999-07-08

2000-10-31

Picardat, Kevin M.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438597, 438637, 438639, H01L 214763

Patent

active

061402206

ABSTRACT:
An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

REFERENCES:
patent: 5466639 (1995-11-01), Ireland
patent: 5612254 (1997-03-01), Mu et al.
patent: 5689140 (1997-11-01), Shoda
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5753967 (1998-05-01), Lin
patent: 6001735 (1999-12-01), Tsaz

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