Dual damascene process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S624000, C438S625000, C438S640000, C438S702000, C438S703000, C438S717000, C257SE21232, C257SE21233, C257SE21579, C257SE21585

Reexamination Certificate

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08062971

ABSTRACT:
Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

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patent: 2006/0216926 (2006-09-01), Ye et al.
patent: 2009/0200683 (2009-08-01), Colburn et al.

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