Dual damascene process

Details Dual damascene process Dual damascene process

1997-06-12

1998-09-01

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438633, 438640, 438740, H01L 2128

Patent

active

058010947

ABSTRACT:
A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.

REFERENCES:
patent: 4372034 (1983-02-01), Bohr
patent: 4560034 (1985-12-01), Bukhman et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 5246882 (1993-09-01), Hartmann
patent: 5466639 (1995-11-01), Ireland
patent: 5635423 (1997-06-01), Huang et al.

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