Dual damascene pattern liner

Details Dual damascene pattern liner Dual damascene pattern liner

2006-01-10

2006-01-10

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S675000

Reexamination Certificate

active

06984580

ABSTRACT:
An embodiment of the invention is a dual damascene layer13of an integrated circuit2containing a dual damascene pattern liner21. Another embodiment of the invention is a method of manufacturing dual damascene layer13where a dual damascene pattern liner21is formed over a cap layer25and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer13where a dual damascene pattern liner21is formed over a cap layer25and within trench spaces.

REFERENCES:
patent: 6319809 (2001-11-01), Chang et al.
patent: 6372647 (2002-04-01), Lu et al.
patent: 6908846 (2005-06-01), McMillin et al.
patent: 2002/0081855 (2002-06-01), Jiang et al.
patent: 2004/0084774 (2004-05-01), Li et al.
S. Satyanarayana et al., “A Solution to Resist Poisoning in the Integration of 248 and 193 nm Photoresist with Low-k Dielectric Materials” Society of Photo-Optical Instrumentation Engineers, Santa Clara, California, Mar. 2002.

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