Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-08-16
2005-08-16
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S631000, C438S700000
Reexamination Certificate
active
06930038
ABSTRACT:
A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.
REFERENCES:
patent: 5420078 (1995-05-01), Sikora
patent: 6042999 (2000-03-01), Lin et al.
patent: 6121130 (2000-09-01), Chua et al.
patent: 6319815 (2001-11-01), Iguchi et al.
patent: 6362093 (2002-03-01), Jang et al.
Chen Hsueh-Chung
Lin Chingfu
J.C. Patents
Novacek Christy
United Microelectronics Corp.
Zarabian Amir
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