Dual damascene method for ultra low K dielectrics

Details Dual damascene method for ultra low K dielectrics Dual damascene method for ultra low K dielectrics

2006-08-22

2006-08-22

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000

Reexamination Certificate

active

07094683

ABSTRACT:
A method for forming a dual damascene opening to protect a low-K dielectric insulating layer including providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack layer comprising at least one dielectric insulating layer over the at least one dielectric insulating to seal the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; photolithographically patterning and etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; and, etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.

REFERENCES:
patent: 5840203 (1998-11-01), Peng
patent: 6323121 (2001-11-01), Liu et al.
patent: 6576562 (2003-06-01), Ohuchi et al.

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