Dual-damascene metal wiring patterns for integrated circuit...

Details Dual-damascene metal wiring patterns for integrated circuit... Dual-damascene metal wiring patterns for integrated circuit...

2006-05-31

2009-06-23

Lebentritt, Michael S (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S640000, C257S751000, C257S760000, C257S762000, C257S763000, C257SE21577, C257SE21579, C257SE23144, C257SE23145, C257SE23161

Reexamination Certificate

active

07550822

ABSTRACT:
Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

REFERENCES:
patent: 6756672 (2004-06-01), You et al.
patent: 2002/0155700 (2002-10-01), Chen et al.
patent: 2002/0185671 (2002-12-01), Kim
patent: 2004/0063310 (2004-04-01), Ngo et al.
patent: 2000-323571 (2000-11-01), None
patent: 1020010061583 (2001-07-01), None

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