Dual damascene manufacturing process

Details Dual damascene manufacturing process Dual damascene manufacturing process

2000-11-06

2003-06-17

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S671000, C438S737000

Reexamination Certificate

active

06579790

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89122540, filed Oct. 26, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing the multi-level interconnects of an integrated circuit. More particularly, the present invention relates to a dual damascene manufacturing process.
2. Description of Related Art
Dual damascene process is a technique of forming vias and interconnects for connecting devices in an integrated circuit. The dual damascene process includes forming an insulation layer over a substrate. After planarizing the upper surface of the insulation layer, the insulation layer is etched according to predetermined metal wiring pattern and positions of vias. Ultimately, trenches and via openings are formed. Subsequently, metallic material is deposited into the trenches and the openings to form a metallic layer, thereby forming metallic conductive wires and vias concurrently. Finally, chemical-mechanical polishing (CMP) is conducted to planarize device surface.
The dual damascene process can prevent overlay errors and process bias problems caused by forming the vias and then the metallic conductive wires in a conventional photolithography. Since vias and interconnects formed by a dual damascene process has greater reliability, most semiconductor manufacturers prefer the process over other processes especially for producing highly integrated circuits.
FIGS. 1A through 1C
are schematic cross-sectional views showing the progression of steps for fabricating a conventional dual damascene structure.
As shown in
FIG. 1A
, a dielectric layer
104
is formed over a substrate
100
having a metallic layer
102
therein. A patterned photoresist layer
106
that exposes a portion of the dielectric layer
104
is formed over the dielectric layer
104
.
As shown in
FIG. 1B
, a portion of the dielectric layer
104
is removed using the patterned photoresist layer
106
(as shown in
FIG. 1A
) as a mask until a portion of the metallic layer
102
is exposed. The dielectric layer
104
is thereby converted into a dielectric layer
104
a
with a via opening
108
therein. The patterned photoresist layer
106
is removed and then another patterned photoresist layer
110
is formed over the substrate
100
.
As shown in
FIG. 1C
, a portion of the dielectric layer
104
a
is removed using the patterned photoresist layer
110
(as shown in
FIG. 1B
) as a mask. Ultimately, the dielectric layer
104
a
is converted into a dielectric layer
104
b
having both a via opening
108
and a conductive wire trench
112
. The via opening
108
and the conductive wire trench
112
together constitute a dual damascene opening
114
. Finally, the patterned photoresist layer
110
is also removed.
In the conventional dual damascene process, altogether two patterned photoresist layers has to be formed so that two photolithographic and etching processes and two photoresist removal steps have to be executed as well. In addition, some photoresist residue of the second patterned photoresist layer
110
may still cling to the interior of the via opening
108
. Hence, electrical properties of the conductive material subsequently deposited into the via opening
108
may be affected.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of fabricating a dual damascene structural opening in a dielectric layer above a substrate. A first photoresist layer having a first opening therein is formed over the dielectric layer. The first opening exposes the dielectric layer at a position where a via is desired. A buffer layer is formed over the first photoresist layer. A second photoresist layer having a second opening therein is formed over the first photoresist layer. The second opening exposes the area where a conductive wire is desired. The first opening and the second opening together form a metallic interconnect structure. Using the first and the second photoresist layer as a mask, a dual damascene structural opening that includes a via opening and a conductive wire trench is formed in the dielectric layer.
According to this invention, a first photoresist layer having a pattern of via openings and a second photoresist layer having a pattern of conductive wire trenches are sequentially formed over the dielectric layer. The first and the second photoresist layer are then used as an etching mask in the production of a dual damascene opening in the dielectric layer.
Since metal interconnect structures (dual damascene opening structure) are directly formed in the two photoresist layers, only one etching operation and one photoresist removal are required after a dual damascene opening is formed in the dielectric layer. Hence, the fabrication process is very much simplified.
In addition, a buffer layer is formed between the first and the second photoresist layer. Since the buffer layer has hydrophilic property, pattern on the first photoresist layer is unaffected by the formation of the second photoresist layer. Moreover, the hydrophilic buffer layer not covered by the second photoresist layer can be removed by developer and cleaning agent when processing the second photoresist layer.
Furthermore, by controlling the etching selectivity between the photoresist layer and the dielectric layer and thickness of the photoresist layer, a dual damascene structure is easily formed with or without an etching stop layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4370405 (1983-01-01), O'Toole et al.
patent: 5126231 (1992-06-01), Levy
patent: 5935762 (1999-08-01), Dai et al.
patent: 6326300 (2001-12-01), Liu et al.
patent: 6329062 (2001-12-01), Gaynor

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