Dual damascene manufacturing process

Details Dual damascene manufacturing process Dual damascene manufacturing process

1998-09-24

2001-01-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S620000, C438S622000, C438S627000, C438S628000, C438S629000, C438S633000, C438S637000, C438S643000, C438S644000, C438S645000, C438S648000, C438S653000, C438S654000, C438S656000, C438S666000, C438S672000, C438S675000, C438S685000, C438S677000, C438S688000

Reexamination Certificate

active

06174804

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87108191, filed May 26, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing multi-level interconnects in semiconductor manufacture. More particularly, the present invention relates to a method of manufacturing multi-level interconnects using a dual damascene process.
2. Description of Related Art
A typical integrated circuit comprises various devices and components. These devices or components are typically insulated by an isolation structure. To electrically connect certain parts of the devices or component, an interconnect is commonly used. In the conventional method of manufacturing interconnects, a metallic layer is deposited over a substrate. A portion of the metallic layer is etched away to form a desired metallic wiring pattern. The metallic wiring pattern is then covered by an insulation layer to is to avoid any unwanted connection to other conductive part of layer. A vertical via hole is formed through the insulation layer to electrically connect the metallic wiring layer. In general, an inter-metal dielectric (IMD) layer is used as an insulation layer to isolate the metallic layer other metallic layer or metallic wiring. The connection between the metallic layer and other metallic layer or metallic wiring is achieved through a vertical via.
At present, two methods of fabricating interconnects such as plugs or vias are used in the semiconductor industry. The first method uses two separate stages for forming the interconnects. A dielectric layer is formed over a first metallic layer, and then a photoresist layer is deposited over the dielectric layer. Etching techniques are used to form a via hole, and then a conductive material is deposited into the via holes to form a via for electrical connection. A second metallic layer is deposited over the dielectric layer followed by the patterning of the second metallic layer.
This second method is a dual damascene process. In the conventional dual damascene process, an insulation layer is first formed over a substrate structure, and then the insulation layer is planarized. According to the required metallic wiring pattern and positions of vias, the insulating layer is etched to form horizontal trenches and vertical via holes. In other words, the lower portion of the insulating layer is etched to expose some of the device regions or portions of the metallic lines below, thereby to form a vertical via hole. The upper portion of the insulating layer is also etched to form a horizontal trench. A metallic material is then deposited over the substrate structure to fill the horizontal trench and the via hole at the same. Chemical-mechanical polishing (CMP) method is used to planarize the surfaces of the devices, and then another dual damascene process can be carried out again. Since two metal-filling operations for forming the respective horizontal trenches and vertical via holes are combined into a single operation, the operation is referred to as a dual damascene process.
FIGS. 1A through 1I
are cross-sectional views showing the progression of manufacturing steps in producing interconnects using a conventional dual damascene process.
As shown in
FIG. 1A
, a substrate structure
100
having a planar surface is provided. For clarity, devices within the substrate structure
100
are not sketched. A metallic layer
101
is formed over the substrate structure
100
. A patterned photoresist layer
104
is formed over the metallic layer
101
. The patterned photoresist layer
104
covers regions above the metallic layer
101
where metallic lines are desired.
As shown in
FIG. 1B
, using the photoresist layer
104
as a mask, the metallic layer
101
is etched. For example, a reactive ion etching (RIE) method is used to etch away a portion of the metallic layer
101
forming metallic lines
101
a
,
101
b
and
101
c
and exposing the substrate structure
100
below. Subsequently, the photoresist layer
104
is removed.
In
FIG. 1C
, an insulation layer
105
, for example, a silicon oxide layer is deposited over the substrate structure
100
. Excess insulation layer
105
above the metal lines
101
a
,
101
b
and
101
c
are removed using, for example, a chemical-mechanical polishing (CMP). Hence, the top surface of the metal lines
101
a
,
101
b
and
101
c
are exposed.
In
FIG. 1D
, another insulation layer
106
, for example, a silicon oxide layer are deposited over the substrate structure
100
and covering the metal lines
101
a
,
101
b
and
101
c
and the insulation layer
105
. The insulation layer
106
has a thickness roughly equals to the vertical height of subsequently formed metal plugs. After that, the insulation layer
106
is planarized, and then an etching stop layer
108
, for example, a silicon nitride layer is deposited over the insulation layer
106
. Subsequently, another patterned photoresist layer
114
is formed over the etching stop layer
108
. The patterned photoresist layer
114
exposes regions on the etching stop layer where vias for extending to the respective metal lines
101
a
and
101
c
are desired.
In
FIG. 1E
, using the photoresist layer
114
as a mask, the silicon nitride layer
108
is etched. For example, using a reactive ion etching (RIE) method, openings
113
and
123
are formed in the etching stop layer
108
a
. The openings
113
and
123
exposes a portion of the insulation layer
106
in regions that correspond to the locations where vias leading to the metal lines
101
a
and
101
c
are desired. Subsequently, the photoresist layer
114
is removed.
In
FIG. 1F
, a third insulation layer
116
, for example, a silicon oxide layer is deposited over the etching stop layer
108
a
. The third insulation layer
116
has a thickness roughly equal to the thickness of the horizontal trenches after the dual damascene structure is formed. Thereafter, a third patterned photoresist layer
124
is formed over the insulation layer
116
. The third patterned photoresist layer
124
exposes a portion of the insulation layer
116
in regions that correspond to the locations where the final horizontal trenches that have connections with the metal lines
101
a
and
101
c
are desired.
In
FIG. 1G
, using the third photoresist layer
124
as a mask, the third insulation layer
116
is etched. For example, a reactive ion etching (RIE) is used to etch out horizontal trenches
115
a
and
125
a
in the insulation layer
116
where metal lines will be formed. A portion of the horizontal trenches
115
a
and
125
a
are aligned over the subsequently formed via holes
115
b
and
125
b
respectively. Thereafter, the insulation layer
106
a
is etched to form via holes
115
b
and
125
b
that exposes the respective metal lines
101
a
and
101
c
. Due to the presence of the etching stop layer
108
a
, a top-wide/bottom-narrow type of openings such as
115
and
125
can be formed by using an etchant having a high etching selectivity for silicon oxide in the etching operation. Subsequently, the photoresist layer
124
is removed.
In
FIG. 1H
, a conformal glue/barrier layer
122
is deposited over the horizontal trenches
115
a
and
125
a
as well as the vertical via holes
115
b
and
125
b
. The conformal glue/barrier layer
122
serves to increase adhesion of subsequently deposited metal or other materials. Thereafter, a metallic layer
121
is deposited over the insulation layer
116
a
and filling the horizontal trenches
115
a
and
125
a
as well as the vertical via holes
115
b
and
125
b.
In
FIG. 1I
, a chemical-mechanical polishing method is used to remove redundant portions of the metallic layer
121
above the insulation layer
116
a
exposing the insulation layer
116
a
. Hence, dual damascene structures
121
a
and
121
b
are formed.
In the above dual damascene process of forming metal interconnects such as contact vias or plugs, complicated steps

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