Dual-damascene interconnects without an etch stop layer by...

Details Dual-damascene interconnects without an etch stop layer by... Dual-damascene interconnects without an etch stop layer by...

2006-01-31

2006-01-31

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S622000, C257S759000

Reexamination Certificate

active

06992391

ABSTRACT:
A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

REFERENCES:
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patent: 6287955 (2001-09-01), Wang et al.
patent: 6287961 (2001-09-01), Liu et al.
patent: 6395632 (2002-05-01), Farrar
patent: 6576550 (2003-06-01), Brase et al.
patent: 2002/0024150 (2002-02-01), Farrar
patent: 2003/0001240 (2003-01-01), Whitechair et al.
patent: 0 945 900 (1999-09-01), None
patent: WO 00/10202 (2000-02-01), None
Int'l Search Report, Int'l Application No. PCT/US02/31159, mailed Jul. 11, 2003, 5 pages.

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