Dual damascene interconnections having low K layer with...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S618000, C438S687000

Reexamination Certificate

active

11034309

ABSTRACT:
A method and apparatus is provided for fabricating a dual damascene interconnection. The method begins by forming on a substrate a dielectric layer that includes an organosilicon material, forming a via photoresist pattern over the dielectric layer, and etching a via in the dielectric layer using the via photoresist pattern as an etch mask. The via photoresist pattern is removed and a trench photoresist pattern is formed over the dielectric layer. A trench, connected to the via, is etched in the dielectric layer using the trench photoresist pattern as an etch mask. The trench photoresist pattern is removed and carbon ions are implanted into exposed surfaces of the via and the trench. A barrier layer is formed that overlies the via and the trench. Finally, interconnections are completed by filling the trench and the via with copper.

REFERENCES:
patent: 2001/0014534 (2001-08-01), Aoki et al.
patent: 2003/0130147 (2003-07-01), Koito et al.
patent: 2003/0235996 (2003-12-01), Leon et al.
patent: 2004/0050406 (2004-03-01), Sehgal
patent: 2004/0053498 (2004-03-01), Kaji et al.
patent: 2004/0087166 (2004-05-01), Morrow

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