Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-09-18
2007-09-18
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S628000, C438S634000
Reexamination Certificate
active
11024657
ABSTRACT:
A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual damascene interconnection includes a lower metal interconnection film, an intermetal insulating film having a via hole and a trench and formed on the lower metal interconnection film, first and second insulative spacer films formed on sidewalls of the via hole and the trench, respectively, a barrier metal layer covering the first and second insulative spacer films and the lower metal interconnection film in the via hole and the trench, and an upper metal interconnection film formed on the barrier metal layer, the via hole and the trench being filled with the upper metal interconnection film.
REFERENCES:
patent: 2001/0049195 (2001-12-01), Chooi et al.
patent: 2005/0263892 (2005-12-01), Chun
patent: 2000-91429 (2000-03-01), None
Dongbu Electronics Co. Ltd.
Lowe Hauptman & Ham & Berner, LLP
Perkins Pamela E
Wilczewski M.
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