Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-03-10
2001-10-02
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S759000
Reexamination Certificate
active
06297554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure of a dielectric layer between two adjacent wiring lines. More particularly, the invention relates to the structure of a dielectric layer that can reduce the parasitic capacitance between two coplanar copper wiring lines.
2. Description of the Prior Art
Resistance-capacitance (RC) time delay is a phenomenon that is caused by adjacent metallic wiring lines in which each line is carrying an electric current, and it is a serious problem in multi-level metalization processes for manufacturing integrated circuits (IC). RC time delays usually lead to reduced response and poor electrical performance of an IC. The response and performance become worse as the spacing between two adjacent metallic wiring lines decreases.
RC time delay is a product of the resistance R of the metallic wiring lines and the parasitic capacitance C formed between them. Minimal RC time delays are desirable. In essence, there are two approaches to reduce RC time delay: a) using conductive materials with a lower resistance as a wiring line or, b) reducing the parasitic capacitance.
Obviously, copper is a good choice owing to its low resistance (1.67 &mgr;&OHgr;-cm) instead of Al—Cu(5%) alloy which is mostly commonly used in current multilevel metalization processes. However, with the ever-increasing demand on performance, changing the metallic material appears to be inadequate to support future requirements. Consequently, some organic dielectric materials with low dielectric constants, such as polyimide (PI) and HSQ (hydrogen silsequioxane) etc., are rapidly coming into use to reduce parasitic capacitance. Unfortunately, most organic dielectric materials have metal adhesion issues and stability problems in a thermal environment.
SUMMARY OF THE INVENTION
It is therefore a primary objective of this invention to provide an improved structure of a dielectric layer between adjacent copper wiring lines to reduce the parasitic capacitance between them, thereby alleviating RC time delays.
According to this invention, the structure of a dielectric layer made of silicon oxide is defined. The structure lies between adjacent coplanar copper wiring lines on a semiconductor wafer. The copper wiring lines are formed in the dielectric layer using a well-known dual damascene process. The structure of the dielectric layer according to this invention comprises at least one trench in the surface of the dielectric layer, an insulating layer in the trench and at least one void in the insulating layer. The void is used to reduce the effective dielectric constant of the dielectric layer so as to reduce the parasitic capacitance between the two adjacent copper wiring lines.
According to one aspect of this invention, the structure of the dielectric layer between the two adjacent copper wiring lines comprises at least one trench with an aspect ratio greater than 3.5. At least one void is in the insulating layer of the trench. The effective dielectric constant is significantly reduced since the relative dielectric constant of air in the void is approximately 1.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5548159 (1996-08-01), Jeng
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.
patent: 5847464 (1998-12-01), Singh et al.
patent: 6022802 (2000-12-01), Jang
patent: 6025260 (2000-02-01), Lien et al.
patent: 6077767 (2000-06-01), Hwang
patent: 6090698 (2000-07-01), Lee
patent: 6091149 (2000-07-01), Hause et al.
patent: 6159842 (2000-12-01), Chang et al.
patent: 6159845 (2000-12-01), Yew et al.
Cruz Lourdes
Hsu Winston
Lee Eddie
United Microelectronics Corp.
LandOfFree
Dual damascene interconnect structure with reduced parasitic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual damascene interconnect structure with reduced parasitic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene interconnect structure with reduced parasitic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2610960