Dual damascene interconnect structure with improved electro...

Details Dual damascene interconnect structure with improved electro... Dual damascene interconnect structure with improved electro...

2006-04-25

2006-04-25

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S672000, C438S640000

Reexamination Certificate

active

07033929

ABSTRACT:
A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

REFERENCES:
patent: 6207577 (2001-03-01), Wang et al.
patent: 6211063 (2001-04-01), Liu et al.
patent: 6271117 (2001-08-01), Cherng
patent: 6294465 (2001-09-01), Hernandez et al.
patent: 6461955 (2002-10-01), Tsu et al.
patent: 6482733 (2002-11-01), Raaijmakers et al.

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