Dual damascene interconnect process with borderless contact

Details Dual damascene interconnect process with borderless contact Dual damascene interconnect process with borderless contact

1998-07-13

2000-02-01

Chang, Joni

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438620, 438624, 438626, 438628, 438633, 438637, 438638, 438644, 438654, 438671, 438672, H01L 214763

Patent

active

060202556

ABSTRACT:
A dual damascene process is disclosed for forming contact and via interconnects without borders. A nitride layer is first formed on a dielectric layer to function as a hard-mask. Metal line trench is first etched into the nitride layer and then into the dielectric layer. Then, a second photoresist layer is used to pattern contact or via hole over line trench opening and the dielectric layer is further etched through the line trench into the dielectric layer until the substructure of the substrate is reached. It is disclosed that by using the nitride layer as a hard-mask, the registration or alignment tolerance between the contact/via hole pattern and the metal line pattern can be relaxed substantially and not use a border as is conventionally practiced in order to assure proper registration between the patterns. The borderless interconnect is achieved by filling the composite line opening and the hole opening with metal and chemical mechanical polishing. The process enables cost reduction and productivity in the semiconductor manufacturing line.

REFERENCES:
patent: 5244837 (1993-09-01), Dennison
patent: 5422309 (1995-06-01), Zettler et al.
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5529953 (1996-06-01), Shoda
patent: 5565707 (1996-10-01), Colgan et al.
patent: 5604156 (1997-02-01), Cheng
patent: 5654589 (1997-08-01), Huang et al.
patent: 5891799 (1999-04-01), Tsui
patent: 5925933 (1999-07-01), Colgan et al.
patent: 5935868 (1999-08-01), Fang et al.
patent: 5946601 (1999-08-01), Wong et al.
Chang et al, "VLSI Technology" The McGraw-Hill Companies Inc. 1996, p 446-447.

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