Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-30
2001-06-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S672000, C438S638000
Reexamination Certificate
active
06251770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to dielectric structures, and more particularly to dielectric structures for dual-damascene applications.
2. Description of the Related Art
Semiconductor devices are made from multi-layer structures that are fabricated on semiconductor wafers. Of great importance to the multi-layer structures is the dielectric materials used in between metallization interconnect lines. In dual-damascene applications, the metallization interconnect lines are defined in trenches that are etched into dielectric layers. Typically, the interconnect metallization is a copper (Cu) material, and the conductive vias are also integrally formed of Cu. As is known to those skilled in the art, there are three general techniques for fabricating metallization interconnect lines and conductive vias. The techniques include: (i) a via first fabrication; (ii) self-aligned fabrication; and (iii) trench first fabrication.
As the demand for faster device speeds continue to increase, fabrication and design engineers have been implementing lower dielectric constant materials. Typically, the speed of an interconnect structure is characterized in terms of RC (resistance/capacitance) delays. Lower dielectric constant materials help in reducing inter-metal capacitance, and therefore, results in reduced delays and faster devices.
The move toward lower dielectric materials has included the use of both organic as well as inorganic materials. One type of lower dielectric material includes a carbon doped silicon dioxide (C-oxide). C-oxide typically has a dielectric constant of about 3.0 or lower, compared to dielectric constants of about 4.1 for silicon dioxides (e.g., un-doped TEOS). Although lower dielectric constants are achieved using C-oxide, this type of inorganic material poses etching difficulties. These difficulties are primarily due to the fact that C-oxide is partially organic (i.e., due to the carbon) and partially inorganic (i.e., silicon dioxide). Also, etch chemistries are generally optimized for inorganic only or organic only films.
To further describe these difficulties, reference is now made to FIG.
1
. As shown, a dielectric
10
is shown having a copper trench line
12
with a liner barrier
14
. A barrier layer
16
a
is used to prevent copper from diffusing into the dielectric
10
. A first oxide layer
18
a
is deposited over the barrier layer
16
a
, and a trench stopping layer
16
b
is deposited over the first oxide layer
18
a
. A second oxide layer
18
b
is then deposited over the trench stopping layer
16
b
. In cases where the first and second oxide layers
18
a
and
18
b
are un-doped TEOS oxide or fluorine doped oxides, there are well developed etching techniques that provide excellent selectivities to the layers
16
a
and
16
b
. For example, such selectivities are in the range of about 20:1, which therefore enable the thicknesses of the layers
16
a
and
16
b
to be kept at a minimum. This is important because layers
16
, which are typically made of silicon nitride (SiN) or silicon carbide (SiC) have dielectric constant levels as high as about 9. Selectivities in the 20:1 range therefore prevent the barrier layer
16
a
from being prematurely removed when relatively thin layers are formed.
On the other hand, when lower dielectrics such as C-oxide are implemented for oxide layers
18
a
and
18
b
, the selectivity to the barrier layers
16
is reduced to ranges nearing about 5:1. This reduction in selectivity therefore causes the barrier layer
16
a
to be removed at location
30
, thereby exposing the underlying copper line
12
to oxygen. When this happens, increased oxidation of the exposed copper will occur (during ashing operations and the like), which therefore generates higher resistive contacts through via holes
20
. Even though the barrier layer
16
a
will be removed prior to sputtering with a liner barrier, the premature exposure does increase the degree of oxidation. In addition, once the copper is exposed, an amount of copper can be etched and possibly caused to be deposited into the dielectric walls of the via holes
20
. Obviously, if copper material were to be deposited into the inter-metal dielectric, a device may fail to optimally perform in accordance with desired performance specifications.
In view of the foregoing, there is a need for low K dielectric materials for use in dual-damascene applications that etch well and retain high selectivity to copper barrier layer materials.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing inter-metal dielectric structures having improved performance in dual-damascene applications. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making a dielectric structure for dual-damascene applications over a substrate is disclosed. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred embodiment, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, wherein the via is within the trench. In one specific example, the inorganic dielectric layer can be an un-doped PECVD TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide or other low K dielectric materials.
In another embodiment, a method for making a multi-layer inter-metal dielectric over a substrate is disclosed. The method includes: (a) forming a barrier layer over the substrate; (b) forming a silicon dioxide layer over the barrier layer; (c) forming a low K dielectric layer over the silicon dioxide layer; (d) forming a trench through the low K dielectric layer; and (e) forming a via in the trench extending to the barrier layer. The forming of the trench is performed using a first etch chemistry and the forming of the via is performed using a second chemistry that is highly selective to the barrier layer and optimized to etch through the silicon dioxide layer.
In yet a further embodiment, a method of making a dielectric layer for use in dual-damascene applications is disclosed. The method includes providing a substrate, depositing a barrier layer over the substrate, and depositing a dopant varying oxide layer over the barrier layer. The depositing of the dopant varying oxide layer includes: (a) depositing in a chemical vapor deposition chamber an initial amount of un-doped oxide over the barrier layer; and (b) introducing an increasing amount of carbon into the chemical vapor deposition chamber, such that a topmost portion of the dopant varying oxide layer has a lower dielectric constant than the initial amount of un-doped oxide.
In still another embodiment, a multi-layer dielectric layer over a substrate for use in dual-damascene applications is disclosed. The multi-layer dielectric layer includes: (a) a barrier layer that is disposed over the substrate; (b) an inorganic dielectric layer that is disposed over the barrier layer; and (c) a low dielectric constant layer that is disposed over the inorganic dielectric layer. The inorganic dielectric layer is configured to receive metallization line trenches and the low dielectric constant layer is configured to receive vias during a dual-damascene process.
Advantageously, the ability to achieve high selectivity to the barrier layer during the via etch will allow the barrier layer thickness to be decreased, thus lowering the overall inter-layer capacitance. Further, the ability to achieve this selectivity during the via etch will also improve line depth uniformity control. Furthermore, manufacturing costs will be lowered and throughput increased
Archer Timothy M.
Benzing Jeffrey C.
Bright Nicolas J.
Hemker Dave J.
MacWilliams Kenneth P.
LAM Research Corp.
Martine Penilla & Kim LLP
Rocchegiani Renzo
Smith Matthew
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