Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-05-09
2004-03-16
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S737000, C438S751000, C438S703000
Reexamination Certificate
active
06706637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming dual damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for efficiently forming dual damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants in a range of from about 1.0 to less than about 3.6. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 4.0 to about 8.0. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, damascene methods do not always provide optimally low dielectric constant dielectric material layer constructions surrounding patterned conductor layers.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively and optimally low dielectric constant dielectric material layer constructions.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within: (1) Jang et al., in U.S. Pat. No. 6,165,898 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer within a microelectronic fabrication absent use of an extrinsic etch stop layer when forming the corresponding trench contiguous with the corresponding via, by employing when forming the dielectric layer a bilayer dielectric layer comprising: (a) a first dielectric material layer which is not susceptible to etching within an oxygen containing plasma, having formed thereupon; (b) a second dielectric material layer which is susceptible to etching within the oxygen containing plasma); (2) Naik et al., in U.S. Pat. No. 6,204,168 (a method for forming within a microelectronic fabrication a damascene structure with enhanced manufacturing efficiency by employing when forming the damascene structure a silicon based photosensitive material layer, such as a plasma polymerized methyl silane (PPMS) material layer, as both a hard mask layer and an etch stop layer); and (3) Tang et al., in U.S. Pat. No. 6,211,092 (a counterbore (i.e., via first) etch method for forming, with enhanced dimensional integrity, a dual damascene aperture within a microelectronic fabrication by employing within the counterbore etch method a plurality of etch steps for forming a via which in part comprises the dual damascene aperture).
Desirable in the art of microelectronic fabrication are additional damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively and optimally low dielectric constant dielectric material layer constructions.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively and optimally low dielectric constant dielectric material construction.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a dual damascene aperture within a dielectric layer. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a first dielectric layer. There is then surface treated the first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Wi
Chen Yu-Huei
Cheng Yao-Yi
Jang Sung-Ming
Yu Chen-Hua
Everhart Caridad
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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