Dual damascene

Details Dual damascene Dual damascene

1998-11-13

2000-06-27

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438687, H01L 214763

Patent

active

06080663&

ABSTRACT:
A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.

REFERENCES:
patent: 5904565 (1999-05-01), Nguyen et al.
patent: 5989623 (1999-11-01), Chen et al.
patent: 6008114 (1999-12-01), Li
patent: 6017817 (2000-01-01), Chung et al.

Affiliated with

Also associated with

Rating

Dual damascene does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1784434