Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-05-06
2000-07-11
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438639, 438666, 438668, H01L 214763
Patent
active
060872527
ABSTRACT:
An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form in a self-aligned process. Therefore, it can successfully avoid misalignment while forming a via plug and an interconnect.
REFERENCES:
patent: 5916823 (1999-06-01), Lou et al.
patent: 6025276 (2000-02-01), Donohoe et al.
patent: 6037194 (2000-03-01), Bronner et al.
Gurley Lynne A.
Huang Jiawei
Niebling John F.
Patents J. C.
United Integrated Circuits Corp.
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